公开(公告)号：US5617575A

公开(公告)日：1997-04-01

申请号：US170743

申请日：1993-12-21

Applicant: Tadayuki Sakakibara ,  Teruo Tanaka ,  Katsuyoshi Kitai ,  Tadaaki Isobe ,  Shigeko Hashimoto ,  Yasuhiro Inagami ,  Yoshiko Tamaki

Inventor： Tadayuki Sakakibara ,  Teruo Tanaka ,  Katsuyoshi Kitai ,  Tadaaki Isobe ,  Shigeko Hashimoto ,  Yasuhiro Inagami ,  Yoshiko Tamaki

IPC: G06F13/18 ,  G06F13/40 ,  G06F12/00 ,  G06F15/16

CPC classification number: G06F13/4027 ,  G06F13/18

Abstract: In a multiprocessor computer system, individual vector processors are provided with priority switching signal control circuits, respectively, and a storage control unit incorporating a priority control circuit. Priority bit information is provided for priority circuits incorporated in the storage control unit. Paths for priority switching signal issued in accordance with a number of requests as generated and types of instruction generating the requests are provided between the priority switching signal control circuits and the priority control circuit of the storage control unit, while paths for the priority switching signal as generated are provided between the priority control circuit and all the priority circuits.

Abstract translation: 在多处理器计算机系统中，分别向各个矢量处理器提供优先切换信号控制电路，以及包含优先控制电路的存储控制单元。 为存储控制单元中包含的优先级电路提供优先级位信息。 在优先切换信号控制电路和存储控制单元的优先控制电路之间，设置根据产生的请求数量和产生请求的指令的类型发出的优先切换信号的路径，而优先切换信号的路径为 生成的优先级控制电路和所有优先级电路之间。

公开(公告)号：US06263406B1

公开(公告)日：2001-07-17

申请号：US09153872

申请日：1998-09-16

Applicant: Kohki Uwano ,  Shigeko Hashimoto ,  Naonobu Sukegawa ,  Tadaaki Isobe ,  Miki Miyaki ,  Tatsuya Ichiki

Inventor： Kohki Uwano ,  Shigeko Hashimoto ,  Naonobu Sukegawa ,  Tadaaki Isobe ,  Miki Miyaki ,  Tatsuya Ichiki

IPC: G06F1300

CPC classification number: G06F12/0815 ,  G06F9/52 ,  G06F9/522

Abstract: Each of processors in a multiprocessor system has a circuit for sending a synchronizing signal to a storage controller (SC) connected thereto when executing a synchronization instruction such as a start, end or barrier synchronization instruction. Each of the SCs has a circuit for notifying the corresponding processor of establishment of a synchronization upon detection of completion of a check to be made by an address management table FAA and of the issuing of necessary cache cancel requests corresponding to a store instruction issued before the synchronization instruction and upon recognition of the fact that all the processors have sent their synchronizing signals and that the issuing of all the cache cancel requests have been complete.

Abstract translation: 多处理器系统中的每个处理器具有用于在执行诸如开始，结束或屏障同步指令之类的同步指令时向连接到其的存储控制器（SC）发送同步信号的电路。 每个SC具有电路，用于在检测到由地址管理表FAA进行的检查的完成以及发出对应于在之前发出的存储指令的必要的高速缓存取消请求之前通知对应的处理器建立同步 同时指令以及所有处理器已经发送了其同步信号以及所有缓存取消请求的发出已经完成的事实。

公开(公告)号：US5857110A

公开(公告)日：1999-01-05

申请号：US760525

申请日：1996-12-05

Applicant: Tadayuki Sakakibara ,  Teruo Tanaka ,  Katsuyoshi Kitai ,  Tadaaki Isobe ,  Shigeko Hashimoto ,  Yasuhiro Inagami ,  Yoshiko Tamaki

Inventor： Tadayuki Sakakibara ,  Teruo Tanaka ,  Katsuyoshi Kitai ,  Tadaaki Isobe ,  Shigeko Hashimoto ,  Yasuhiro Inagami ,  Yoshiko Tamaki

IPC: G06F13/18 ,  G06F13/40 ,  G06F13/00

CPC classification number: G06F13/4027 ,  G06F13/18

Abstract: In a multiprocessor computer system, individual vector processors are provided with priority switching signal control circuits, respectively, and a storage control unit incorporating a priority control circuit. Priority bit information is provided for priority circuits incorporated in the storage control unit. Paths for priority switching signal issued in accordance with a number of requests as generated and types of instruction generating the requests are provided between the priority switching signal control circuits and the priority control circuit of the storage control unit, while paths for the priority switching signal as generated are provided between the priority control circuit and all the priority circuits.

Abstract translation: 在多处理器计算机系统中，分别向各个矢量处理器提供优先切换信号控制电路，以及包含优先控制电路的存储控制单元。 为存储控制单元中包含的优先级电路提供优先级位信息。 在优先切换信号控制电路和存储控制单元的优先控制电路之间，设置根据产生的请求数量和产生请求的指令的类型发出的优先切换信号的路径，而优先切换信号的路径为 生成的优先级控制电路和所有优先级电路之间。

公开(公告)号：US06466988B1

公开(公告)日：2002-10-15

申请号：US09473276

申请日：1999-12-28

Applicant: Naonobu Sukegawa ,  Kouki Uwano ,  Shigeko Hashimoto ,  Masakazu Fukagawa ,  Eiki Kamada

Inventor： Naonobu Sukegawa ,  Kouki Uwano ,  Shigeko Hashimoto ,  Masakazu Fukagawa ,  Eiki Kamada

IPC: G06F1300

CPC classification number: G06F12/0815 ,  G06F12/0822

Abstract: A shared main memory type multiprocessor is arranged to have a switch connection type. The multiprocessor prepares an instruction for outputting a synchronization transaction. When each CPU executes this instruction, after all the transactions of the preceding instructions are output, the synchronization transaction is output to the main memory and the coherence controller. By the synchronization transaction, the main memory serializes the memory accesses and the coherence controller guarantees the completion of the cache coherence control. This makes it possible to serialize the memory accesses and guarantee the completion of the cache coherence control at the same time.

Abstract translation: 共享的主存储器型多处理器被布置成具有开关连接类型。 多处理器准备用于输出同步事务的指令。 当每个CPU执行该指令时，在输出上述指令的所有事务之后，将同步事务输出到主存储器和相干控制器。 通过同步事务，主存储器将存储器访问序列化，并且相干控制器保证高速缓存一致性控制的完成。 这使得可以同时序列化存储器访问并保证高速缓存一致性控制的完成。