公开(公告)号：US5864494A

公开(公告)日：1999-01-26

申请号：US906519

申请日：1997-08-05

申请人： Shinji Toyoyama ,  Yuichi Sato

发明人： Shinji Toyoyama ,  Yuichi Sato

IPC分类号： H04N19/60 ,  G06F17/14 ,  H03M7/30 ,  H04N1/41 ,  H04N19/42 ,  H04N19/625

CPC分类号： G06F17/147

摘要： A discrete cosine transformer capable of real time processing without a multiplier having small circuit scale and small power consumption includes an adder/subtractor receiving a plurality of image data items for outputting a plurality of image data item addition/subtraction values in accordance with a prescribed rule, a bit distributor connected to the adder/subtractor, receiving the plurality of image data item addition/subtraction values for outputting a plurality of bit trains consisting of bits at same bit position of the plurality of image data item addition/subtraction values, a selection signal generating circuit for successively generating a selection signal of a DCT coefficient, and a DCT coefficient generating circuit connected to the bit distributor and to the selection signal generating circuit, receiving a plurality of bit trains and responsive to the successively generated selection signal, for performing calculation of the DCT coefficient in time-divisional manner.

摘要翻译： 能够进行实时处理的离散余弦变换器，而不需要具有小电路规模和小功耗的乘法器，包括：加法器/减法器，接收多个图像数据项，用于根据规定的规则输出多个图像数据项加法/减法值 连接到加法器/减法器的位分配器，接收多个图像数据项加法/减法值，用于输出由多个图像数据项加法/减法值中的相同位位置的位组成的多个位串，选择 信号发生电路，用于连续产生DCT系数的选择信号;以及DCT系数产生电路，连接到比特分配器和选择信号发生电路，接收多个比特串并响应于连续生成的选择信号，以执行 以时分方式计算DCT系数。

公开(公告)号：US5298485A

公开(公告)日：1994-03-29

申请号：US983290

申请日：1992-11-30

申请人： Shoei Kataoka ,  Hiroya Sato ,  Shuhei Tsuchimoto ,  Hideo Nojima ,  Shinji Toyoyama ,  Masayoshi Koba ,  Nobuo Hashizume ,  Eizo Ohno ,  Susumu Saitoh

发明人： Shoei Kataoka ,  Hiroya Sato ,  Shuhei Tsuchimoto ,  Hideo Nojima ,  Shinji Toyoyama ,  Masayoshi Koba ,  Nobuo Hashizume ,  Eizo Ohno ,  Susumu Saitoh

IPC分类号： H01L39/18 ,  H03K19/195 ,  H03K17/92

CPC分类号： H01L39/18 ,  Y10S505/858 ,  Y10S505/86

摘要： A logic circuit device includes a superconductive body formed of a ceramic superconductive material. The ceramic superconductive material has random grain boundaries which act as weak couplings. The ceramic superconductive material also has a magneto-resistive property. There is at least one conductor arranged near the ceramic superconductive body in order to exert a magnetic field on the ceramic superconductive body. The ceramic superconductive body changes its resistance in response to the magnetic field generated by the conductor. The ceramic superconductive body can be used as part of a logic circuit.

摘要翻译： 逻辑电路器件包括由陶瓷超导材料形成的超导体。 陶瓷超导材料具有作为弱耦合的随机晶界。 陶瓷超导材料也具有磁阻特性。 至少有一个布置在陶瓷超导体附近的导体，以便在陶瓷超导体上施加磁场。 陶瓷超导体响应于导体产生的磁场而改变其电阻。 陶瓷超导体可以用作逻辑电路的一部分。

公开(公告)号：US5223446A

公开(公告)日：1993-06-29

申请号：US777668

申请日：1991-10-16

申请人： Toshiaki Miyajima ,  Shinji Toyoyama ,  Masayoshi Koba

发明人： Toshiaki Miyajima ,  Shinji Toyoyama ,  Masayoshi Koba

IPC分类号： H01L27/144 ,  H03K17/785

CPC分类号： H01L27/1443 ,  H03K17/785

摘要： A semiconductor device is disclosed which comprises a normally-off first MOSFET, a normally-off second MOSFET connected between the gate and source of the first MOSFET, a diode connected between the gate and source of the second MOSFET, a resistor and an optoelectric transducer array, both of which are connected in parallel with each other between the gate and drain of the second MOSFET, wherein all of the components are formed on a single semiconductor chip. Also disclosed is a semiconductor device comprising a normally-off first MOSFET, a normally-on second MOSFET connected between the gate and source of the first MOSFET, a first resistor and a diode, both of which are connected in series between the source and drain of the second MOSFET, a second resistor connected between the gate and source of the second MOSFET, an optoelectric transducer array connected between the gate of the second MOSFET and the terminal which is positioned between the first resistor and the diode, wherein all of the components are formed on a single semiconductor chip.Further disclosed is a method for manufacturing a semiconductor device comprising a normally-off first MOSFET, a normally-off second MOSFET connected between the gate and source of the first MOSFET, a diode connected between the gate and source of the second MOSFET, a resistor and an optoelectric transducer array, both of which are connected in parallel with each other between the gate and drain of the second MOSFET.

摘要翻译： 公开了一种半导体器件，其包括常闭第一MOSFET，连接在第一MOSFET的栅极和源极之间的常关的第二MOSFET，连接在第二MOSFET的栅极和源极之间的二极管，电阻器和光电换能器 阵列，它们都在第二MOSFET的栅极和漏极之间彼此并联连接，其中所有的部件形成在单个半导体芯片上。 还公开了一种半导体器件，包括常闭第一MOSFET，连接在第一MOSFET的栅极和源极之间的常数第二MOSFET，第一电阻器和二极管，两者均串联连接在源极和漏极 连接在第二MOSFET的栅极和源极之间的第二电阻器，连接在第二MOSFET的栅极和位于第一电阻器和二极管之间的端子之间的光电变换器阵列，其中所有部件 形成在单个半导体芯片上。 进一步公开的是一种制造半导体器件的方法，该半导体器件包括常闭第一MOSFET，连接在第一MOSFET的栅极和源极之间的常关的第二MOSFET，连接在第二MOSFET的栅极和源极之间的二极管， 以及光电转换器阵列，它们都在第二MOSFET的栅极和漏极之间彼此并联连接。

公开(公告)号：US06985026B2

公开(公告)日：2006-01-10

申请号：US10485988

申请日：2002-08-02

申请人： Shinji Toyoyama

发明人： Shinji Toyoyama

IPC分类号： G05F1/10

CPC分类号： G05F3/242 ,  G05F3/24 ,  H01L27/0251

摘要： In a semiconductor integrated circuit device, a first control signal outputted from the power voltage evaluation circuit controls power voltage of the power voltage generation circuit so that the power voltage becomes lower within a range over which the internal circuit normally operates, while a second control signal outputted from the specified voltage detection circuit controls the power voltage of the power voltage generation circuit so that the power voltage generated by the power voltage generation circuit does not become equal to or higher than a specified voltage. This makes the power voltage as low as possible within the normally operational range of the internal circuit and suppresses increase of the gate current, so that unstable operations and current consumption increase of the MOS transistor can be prevented.

摘要翻译： 在半导体集成电路器件中，从电源电压评估电路输出的第一控制信号控制电源电压产生电路的电源电压，使电源电压在内部电路正常工作的范围内变低，而第二控制信号 从指定的电压检测电路输出，控制电源电压发生电路的电源电压，使得由电源电压产生电路产生的电力电压不变得等于或高于指定的电压。 这使得电力电压在内部电路的正常工作范围内尽可能低，并且抑制栅极电流的增加，从而可以防止MOS晶体管的不稳定操作和电流消耗增加。

公开(公告)号：US06469568B2

公开(公告)日：2002-10-22

申请号：US09742369

申请日：2000-12-22

申请人： Shinji Toyoyama ,  Yuichi Sato

发明人： Shinji Toyoyama ,  Yuichi Sato

IPC分类号： G05F302

CPC分类号： H03K19/0013 ,  H01L27/092 ,  H03K19/0016 ,  H03K2217/0018

摘要： A select circuit switches a connection from a gate terminal of an NMOS transistor or a substrate voltage terminal to a semiconductor substrate or well by a Select signal. At this time, a voltage of the substrate voltage terminal is set to be lower than a gate voltage in an OFF state. Consequently, when the semiconductor substrate or well is connected to the gate terminal in an active state, the off-current can be reduced to 10−10 A/&mgr;m. When the substrate voltage terminal is connected to the semiconductor substrate or well in a standby state, the off-current can be further reduced to 10−12 A/&mgr;m. Thus, leakage currents in the standby state and leakage currents flowing from the power supply voltage terminal to the ground voltage terminal in an active state can be suppressed.

公开(公告)号：US6140944A

公开(公告)日：2000-10-31

申请号：US81516

申请日：1998-05-20

申请人： Shinji Toyoyama

发明人： Shinji Toyoyama

IPC分类号： H04N19/60 ,  H03M7/42 ,  H03M7/46 ,  H04N1/41 ,  H04N19/102 ,  H04N19/136 ,  H04N19/423 ,  H04N19/426 ,  H04N19/625 ,  H04N19/91

CPC分类号： H03M7/42

摘要： A variable-length coding device includes: a code presence/absence determination table storing information concerning whether a code is allocated or not correspondingly to a prescribed region in a region represented by a combination of run data and level data; a first region determination circuit and a second region determination circuit determining whether a pair of run data and level data is contained in the prescribed region; and a run.level pair conversion circuit, a first code table, and a second code table that perform coding, referring to the code presence/absence determination table, if the first region determination circuit and the second region determination circuit determine that the pair of run data and level data is contained in the prescribed region, and that perform coding without referring to the code presence/absence determination table if the first region determination circuit and the second region determination circuit determine that the pair of run data and level data is not contained in the prescribed region.

摘要翻译： 可变长度编码装置包括：代码存在/不存在判定表，存储关于在由运行数据和电平数据的组合表示的区域中对应于规定区域分配的代码的信息; 第一区域确定电路和第二区域确定电路，确定在所述规定区域中是否包含一对行驶数据和电平数据; 以及执行编码的运行级对转换电路，第一代码表和第二代码表，参考代码存在与否确定表，如果第一区域确定电路和第二区域确定电路确定该对 运行数据和电平数据包含在规定区域中，并且如果第一区域确定电路和第二区域确定电路确定一对运行数据和电平数据不是，则执行编码而不参考代码存在/不存在确定表 包含在规定的区域。

公开(公告)号：US08767142B2

公开(公告)日：2014-07-01

申请号：US13704213

申请日：2012-04-02

申请人： Shinji Toyoyama

发明人： Shinji Toyoyama

IPC分类号： G02F1/1333 ,  G02F1/1335

CPC分类号： G02F1/1333 ,  G02F1/133308 ,  G02F1/133608 ,  G02F1/13452 ,  G02F2001/133314 ,  G02F2001/133334 ,  G02F2001/133612 ,  G02F2201/46 ,  G09F9/00

摘要： A liquid crystal display device (1) includes a liquid crystal display panel (2), a metal backlight chassis (4), a metal bezel (13), a printed circuit board (31), an electric conductor (14) via which the metal backlight chassis (4) and a ground land part (31f) of the printed circuit board (31) are electrically connected with each other, and a frame (10) having an insertion hole in which the electric conductor (14) is inserted.

摘要翻译： 液晶显示装置（1）包括液晶显示面板（2），金属背光底盘（4），金属表圈（13），印刷电路板（31），电导体（14） 金属背光源底座（4）和印刷电路板（31）的接地部分（31f）彼此电连接，并且具有插入导电体（14）的插入孔的框架（10）。

公开(公告)号：US20130141664A1

公开(公告)日：2013-06-06

申请号：US13704213

申请日：2012-04-02

申请人： Shinji Toyoyama

发明人： Shinji Toyoyama

IPC分类号： G02F1/1333

CPC分类号： G02F1/1333 ,  G02F1/133308 ,  G02F1/133608 ,  G02F1/13452 ,  G02F2001/133314 ,  G02F2001/133334 ,  G02F2001/133612 ,  G02F2201/46 ,  G09F9/00

摘要： A liquid crystal display device (1) includes a liquid crystal display panel (2), a metal backlight chassis (4), a metal bezel (13), a printed circuit board (31), an electric conductor (14) via which the metal backlight chassis (4) and a ground land part (31f) of the printed circuit board (31) are electrically connected with each other, and a frame (10) having an insertion hole in which the electric conductor (14) is inserted.

摘要翻译： 液晶显示装置（1）包括液晶显示面板（2），金属背光底盘（4），金属表圈（13），印刷电路板（31），电导体（14） 金属背光源底座（4）和印刷电路板（31）的接地部分（31f）彼此电连接，并且具有插入导电体（14）的插入孔的框架（10）。

公开(公告)号：US06775684B1

公开(公告)日：2004-08-10

申请号：US09586596

申请日：2000-06-02

申请人： Shinji Toyoyama ,  Yuichi Sato

发明人： Shinji Toyoyama ,  Yuichi Sato

IPC分类号： G06F1710

CPC分类号： H04B1/7093 ,  G06F17/15

摘要： A digital matched filter has a serial-to-parallel conversion circuit that converts input data fed thereto in serial form into n sets of parallel data and a plurality of delay circuits that each output serial data fed thereto with a delay corresponding to n sets of data. The serial-to-parallel conversion circuit and the delay circuits are each fed with n clocks having different phases, and are composed of delay devices connected in n groups of serially connected delay devices so that the input data is shifted in synchronism with the rising edges of those n clocks. The outputs from the individual delay devices are multiplied by codes by multipliers, and the results of those multiplications are added together and output as output data by an adder.

摘要翻译： 数字匹配滤波器具有串行到并行转换电路，其将以串行形式馈送到其的输入数据转换成n组并行数据和多个延迟电路，每个延迟电路以对应于n组数据的延迟输出馈送到其的串行数据 。 串并转换电路和延迟电路分别馈入具有不同相位的n个时钟，并且由连接在n组串联延迟器件中的延迟器组成，使得输入数据与上升沿同步地移位 的那些n个时钟。 各个延迟装置的输出由乘法器乘以代码，并将这些乘法的结果相加在一起，并通过加法器作为输出数据输出。

公开(公告)号：US06724812B2

公开(公告)日：2004-04-20

申请号：US09725763

申请日：2000-11-30

申请人： Shinji Toyoyama ,  Yuichi Sato

发明人： Shinji Toyoyama ,  Yuichi Sato

IPC分类号： H04B1500

CPC分类号： H04B1/7093

摘要： A matched filter has a circuit calculating an exclusive-OR of two input data, a circuit calculating an exclusive-OR of two codes corresponding to the two input data, respectively, and a correlation processor. The correlation processor, using the exclusive-OR of the two input data, one of the two input data, the exclusive-OR of the two codes, and the code corresponding to one of the two input data, calculates a correlation value of the two input data and the two codes.

摘要翻译： 匹配滤波器具有计算两个输入数据的异或的电路，分别计算与两个输入数据相对应的两个代码的异或的电路和相关处理器。 相关处理器使用两个输入数据的异或，两个输入数据中的一个，两个代码的异或和与两个输入数据之一相对应的代码，计算两者的相关值 输入数据和两个代码。