公开(公告)号：US5526296A

公开(公告)日：1996-06-11

申请号：US339644

申请日：1994-11-14

申请人： Shigeru Nakahara ,  Shinobu Yabuki ,  Ryuichi Satomura

发明人： Shigeru Nakahara ,  Shinobu Yabuki ,  Ryuichi Satomura

IPC分类号： G06F7/38 ,  G06F7/76

CPC分类号： G06F7/764

摘要： A second barrel shifter whose shift amount is equally controlled as that of a first barrel shifter for shifting input data by an optional bit is employed as a mask data generating circuit in a bit field operational arithmetic unit. Areas with transistor trains of the first and second barrel shifters are formed in parallel to an area having the same width as that of a 1-bit storage cell of a register file and shift amount control lines in both barrel shifters are set for common use so as to reduce the area occupied by a chip. In order to increase the processing speed of extracting an optional area of data, the bit field operational arithmetic unit is provided with a circuit for subjecting all bits to signal expansion in No. 0 bit data in parallel to the shift of input data effected by the first barrel shifter. Moreover, barrel shift circuits include left and right shift circuits as n shift circuits for shifting 2.sup.i -bit (i=0, 1, 2, . . . , n-1) data, with n as a positive integer. Consequently, an optional number of bits up to 2.sup.n -bit of input data can thus be shifted by directing fetching n-bit shift control data.

摘要翻译： 第二桶形移位器的移位量被等同地控制为用于通过任选位移位输入数据的第一桶形移位器的移位量被用作位域运算运算单元中的掩模数据产生电路。 具有第一和第二桶形移位器的晶体管列的区域与具有与寄存器堆的1位存储单元的宽度相同的宽度的区域平行地形成，并且两个桶形移位器中的移位量控制线被设置为共同使用， 以减少芯片占用的面积。 为了提高提取可选择的数据区域的处理速度，比特域运算运算单元具有一个电路，用于使所有位在0比特数据中进行信号扩展，并行于由 第一桶移位器。 此外，桶形移位电路包括左移位电路和右移位电路，作为用于移位2i位（i = 0,1,2，...，n-1）数据的n个移位电路，其中n为正整数。 因此，可以通过指定取出n位移位控制数据来移位高达2n位输入数据的可选数量的位。

公开(公告)号：US20100271103A1

公开(公告)日：2010-10-28

申请号：US12429172

申请日：2009-04-23

申请人： Nao Miyamoto ,  Tatsuhiro Aida ,  Shinobu Yabuki

发明人： Nao Miyamoto ,  Tatsuhiro Aida ,  Shinobu Yabuki

IPC分类号： H03L5/00

CPC分类号： H03K3/35613

摘要： When a high-voltage output is Hi, a first N-type transistor and a second P-type transistor are in an OFF state, and a second N-type transistor and a first P-type transistor are in an ON state, where a high voltage is applied to drain-source of the first N-type transistor. In a process to shift the high voltage output to Lo, a gate potential of the first N-type transistor is once put to an intermediate state between VDD and GND to lower a drain-source voltage of the first N-type transistor, then the gate potential is raised to VDD. In this manner, a state where the drain-source voltage of the first N-type transistor is large and also a drain current of the same is large is avoided, so that an On withstand voltage of the level shift circuit is increased, thereby preventing a breakdown.

摘要翻译： 当高电压输出为Hi时，第一N型晶体管和第二P型晶体管处于截止状态，第二N型晶体管和第一P型晶体管处于导通状态，其中a 对第一N型晶体管的漏源施加高电压。 在将高电压输出转换为Lo的过程中，第一N型晶体管的栅极电位曾经被置于VDD和GND之间的中间状态，以降低第一N型晶体管的漏 - 源电压，然后 栅极电位上升到VDD。 以这种方式，避免了第一N型晶体管的漏极 - 源极电压大并且其漏极电流大的状态，使得电平移位电路的导通耐受电压增加，从而防止 分解。

公开(公告)号：US20090072622A1

公开(公告)日：2009-03-19

申请号：US12172426

申请日：2008-07-14

申请人： Akihiko GOTO ,  Nao Miyamoto ,  Shinobu Yabuki ,  Tatsuhiro Aida

发明人： Akihiko GOTO ,  Nao Miyamoto ,  Shinobu Yabuki ,  Tatsuhiro Aida

IPC分类号： H02J3/14

CPC分类号： H03K3/356 ,  G09G3/293 ,  G09G3/296 ,  H03K17/0828 ,  Y10T307/461

摘要： A level shift 9, IGBT1, 2 and a AND element 10 are provided. An output DOUT is controlled to four states Hi/Lo/HiZ/artificial Hi by controlling input signals IN1, IN2, IN3, PULSE_IN. An element is protected from output short circuiting by transferring an output after a fixed time period to an artificial Hi. Furthermore NMOS are connected in parallel between two inverter circuits and the two stage of the inverter circuit is connected to the gate of NMOS. A delay circuit connecting the output of the initial state of the inverter circuit to a drain and the source of the NMOS to GND is connected to PULSE_IN of the level shift 9. Thus it is possible to almost completely eliminate temperature dependency of the delay time.

摘要翻译： 提供电平位移9，IGBT1,2和AND元件10。 通过控制输入信号IN1，IN2，IN3，PULSE_IN，将输出DOUT控制为四个状态Hi / Lo / HiZ /人工Hi。 通过将固定时间段之后的输出传送到人造Hi来保护元件免于输出短路。 此外，NMOS在两个反相器电路之间并联连接，反相器电路的两级连接到NMOS的栅极。 将逆变器电路的初始状态的输出连接到漏极和NMOS至GND的源极的延迟电路连接到电平移位9的PULSE_IN。因此可以几乎完全消除延迟时间的温度依赖性。

公开(公告)号：US5514895A

公开(公告)日：1996-05-07

申请号：US395997

申请日：1995-02-28

申请人： Ken'ichi Kikushima ,  Masaaki Yoshida ,  Shinobu Yabuki

发明人： Ken'ichi Kikushima ,  Masaaki Yoshida ,  Shinobu Yabuki

IPC分类号： H01L23/485 ,  H01L23/528 ,  H01L23/532 ,  H01L27/02 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L23/53257 ,  H01L23/485 ,  H01L23/5286 ,  H01L24/06 ,  H01L27/0207 ,  H01L2224/05554 ,  H01L2924/10253 ,  H01L2924/12036 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14

摘要： In a semiconductor integrated circuit device having cells comprising circuit elements including MISFETs, and a multi-layer wiring structure, wirings of a first layer connected to semiconductor regions of the MISFETs (source and drain regions) are formed almost in the entire area over the regions to shunt the regions. Power supply wiring are formed of second layer wirings. First layer wirings and the semiconductor regions are connected through a plurality of contact holes. The power supply wirings are formed to cover at least part of the semiconductor regions. In accordance with another aspect, macro-cells are formed by basic cells, including a plurality of MISFETs with the direction of gate length aligned in a first direction, regularly arranged in the first direction and in a second intersecting direction. The MISFETs in each basic cell are interconnected by a first-layer signal wiring, basic cells adjacently arranged in the second direction are interconnected by a first-layer signal wiring extending in the second direction, and basic cells adjacently arranged in the first direction are interconnected by a second-layer signal wiring extending in the first direction. The MISFETs in basic cells adjacently arranged in the first direction receive power from a second-layer power wiring located in the same layer of the second-layer signal wiring and extended in the same first direction. A fourth-layer power supply wiring and a fourth-layer signal wiring, both extending in the first direction, are also provided.

公开(公告)号：US07245019B2

公开(公告)日：2007-07-17

申请号：US10647373

申请日：2003-08-26

申请人： Tomoo Murata ,  Shinobu Yabuki ,  Takeo Yamashita

发明人： Tomoo Murata ,  Shinobu Yabuki ,  Takeo Yamashita

IPC分类号： H01L23/52

CPC分类号： H01L27/118 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method of manufacturing a semiconductor device having a first wiring extending in a first direction and a second wiring connected to the first wiring through a connection and extending in a second direction orthogonal to the first direction, the second wiring having a surplus portion projecting from the connection in a direction opposite to the second direction, the first and second wirings are arranged such that a center of the connection is offset in the second direction from a center of the first wiring, and a projecting portion of the first wiring is disposed under the connection.

摘要翻译： 在制造具有沿第一方向延伸的第一布线的半导体器件的方法和通过连接与第一布线连接并沿与​​第一方向正交的第二方向延伸的第二布线的方法中，第二布线具有从 在与第二方向相反的方向上的连接中，第一和第二布线布置成使得连接的中心在距第一布线的中心的第二方向偏移，并且第一布线的突出部分设置在 连接。

公开(公告)号：US5410173A

公开(公告)日：1995-04-25

申请号：US20793

申请日：1993-02-22

申请人： Ken'ichi Kikushima ,  Masaaki Yoshida ,  Shinobu Yabuki

发明人： Ken'ichi Kikushima ,  Masaaki Yoshida ,  Shinobu Yabuki

IPC分类号： H01L23/485 ,  H01L23/528 ,  H01L23/532 ,  H01L27/02 ,  H01L29/78 ,  H01L33/00

CPC分类号： H01L23/53257 ,  H01L23/485 ,  H01L23/5286 ,  H01L24/06 ,  H01L27/0207 ,  H01L2224/05554 ,  H01L2924/10253 ,  H01L2924/12036 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14

摘要： In a semiconductor integrated circuit device having cells comprising circuit elements including MISFETs, and a multi-layer wiring structure, wirings of a first layer connected to semiconductor regions of the MISFETs (source and drain regions) are formed almost in the entire area over the regions to shunt the regions. Power supply wiring are formed of second layer wirings. First layer wirings and the semiconductor regions are connected through a plurality of contact holes. The power supply wirings are formed to cover at least part of the semiconductor regions. In accordance with another aspect, macro-cells are formed by basic cells, including a plurality of MISFETs with the direction of gate length aligned in a first direction, regularly arranged in the first direction and in a second intersecting direction. The MISFETs in each basic cell are interconnected by a first-layer signal wiring, basic cells adjacently arranged in the second direction are interconnected by a first-layer signal wiring extending in the second direction, and basic cells adjacently arranged in the first direction are interconnected by a second-layer signal wiring extending in the first direction. The MISFETs in basic cells adjacently arranged in the first direction receive power from a second-layer power wiring located in the same layer of the second-layer signal wiring and extended in the same first direction. A fourth-layer power supply wiring and a fourth-layer signal wiring, both extending in the first direction, are also provided.

摘要翻译： 在具有包括MISFET和多层布线结构的电路元件的单元的半导体集成电路器件中，连接到MISFET（源极和漏极区域）的半导体区域的第一层的布线几乎在该区域的整个区域中形成 分流区域。 电源布线由第二层布线形成。 第一层布线和半导体区域通过多个接触孔连接。 形成电源布线以覆盖半导体区域的至少一部分。 根据另一方面，宏单元由基本单元形成，包括多个MISFET，其栅极长度方向在第一方向上对齐，在第一方向和第二相交方向上规则地排列。 每个基本单元中的MISFET通过第一层信号布线互连，在第二方向上相邻布置的基本单元通过沿第二方向延伸的第一层信号布线互连，并且在第一方向上相邻布置的基本单元互连 通过沿第一方向延伸的第二层信号线。 在第一方向上相邻布置的基本单元中的MISFET从位于第二层信号布线的同一层的第二层电力布线接收电力并沿相同的第一方向延伸。 还提供了沿第一方向延伸的第四层电源布线和第四层信号布线。