公开(公告)号：US08724388B2

公开(公告)日：2014-05-13

申请号：US13437324

申请日：2012-04-02

申请人： Tio Wei Neo ,  Shivananda Shetty ,  James Pak

发明人： Tio Wei Neo ,  Shivananda Shetty ,  James Pak

IPC分类号： G11C11/34 ,  G11C16/10 ,  G11C11/56

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/14 ,  G11C16/3418

摘要： Embodiments described herein generally relate to programming and erasing a FLASH memory. In an embodiment, a method of programming or erasing the contents of a block of a FLASH memory includes determining a voltage of a pulse based on an age of the block and outputting the pulse to at least a portion of the block. The pulse is used to program or erase the block.

摘要翻译： 本文描述的实施例通常涉及编程和擦除闪速存储器。 在一个实施例中，编程或擦除FLASH存储器的块的内容的方法包括基于块的时间确定脉冲的电压并将该脉冲输出到块的至少一部分。 脉冲用于编程或擦除块。

公开(公告)号：US20130258775A1

公开(公告)日：2013-10-03

申请号：US13437324

申请日：2012-04-02

申请人： Tio Wei NEO ,  Shivananda SHETTY ,  James PAK

发明人： Tio Wei NEO ,  Shivananda SHETTY ,  James PAK

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/14 ,  G11C16/3418

摘要： Embodiments described herein generally relate to programming and erasing a FLASH memory. In an embodiment, a method of programming or erasing the contents of a block of a FLASH memory includes determining a voltage of a pulse based on an age of the block and outputting the pulse to at least a portion of the block. The pulse is used to program or erase the block.

摘要翻译： 本文描述的实施例通常涉及编程和擦除闪速存储器。 在一个实施例中，编程或擦除FLASH存储器的块的内容的方法包括基于块的时间确定脉冲的电压并将该脉冲输出到块的至少一部分。 脉冲用于编程或擦除块。

公开(公告)号：US06941529B1

公开(公告)日：2005-09-06

申请号：US10288959

申请日：2002-11-05

申请人： Shivananda Shetty ,  W. Eugen Hill ,  Mehrdad Mahanpour

发明人： Shivananda Shetty ,  W. Eugen Hill ,  Mehrdad Mahanpour

IPC分类号： G01R31/02 ,  G01R31/305 ,  G01R31/308 ,  G01R31/311 ,  G06F17/50 ,  G06F19/00

CPC分类号： G01R31/308 ,  G01R31/311

摘要： A method and system for verifying an architecture of a semiconductor device is disclosed. The method and system include providing a tester, a detector and an image processing unit. The tester applies at least one voltage to at least one selected portion of the semiconductor device. The at least one voltage is sufficient for the at least one selected portion of the semiconductor device to produce a particular level of radiation. The detector detects the radiation. The image processing unit is coupled with the detector and the tester. The image processing unit captures an image from the detector. The image indicates at least one physical location of the at least one selected portion of the semiconductor device. The architecture of the memory device can be verified by comparing the at least one selected portion of the semiconductor device to the at least one physical location.

摘要翻译： 公开了一种用于验证半导体器件的架构的方法和系统。 该方法和系统包括提供测试器，检测器和图像处理单元。 测试仪将至少一个电压施加到半导体器件的至少一个选定部分。 至少一个电压足以使半导体器件的至少一个选定部分产生特定水平的辐射。 检测器检测辐射。 图像处理单元与检测器和测试器耦合。 图像处理单元从检测器捕获图像。 图像表示半导体器件的至少一个选定部分的至少一个物理位置。 可以通过将半导体器件的至少一个选定部分与至少一个物理位置进行比较来验证存储器件的结构。