公开(公告)号：US20100308385A1

公开(公告)日：2010-12-09

申请号：US12778308

申请日：2010-05-12

Applicant: Shuji Manda ,  Hiroshi Takahashi

Inventor： Shuji Manda ,  Hiroshi Takahashi

IPC: H01L27/146 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/14603 ,  H01L21/823885 ,  H01L27/092 ,  H01L27/14609 ,  H01L27/14612 ,  H01L27/14632 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14689

Abstract: Disclosed herein is a semiconductor device having a vertical MOS transistor having a channel of a first conductivity type and formed by burying a gate electrode in a semiconductor substrate, a planar MOS transistor having a channel of the first conductivity and having a gate electrode formed on the semiconductor substrate, and a planar MOS transistor having a channel of a second conductivity and having a gate electrode formed on the semiconductor substrate, the semiconductor device, including other circuit element(s), other than a transistor, formed either below or above the vertical MOS transistor having the channel of the first conductivity type.

Abstract translation: 本发明公开了一种具有垂直MOS晶体管的半导体器件，其具有第一导电类型的沟道并且通过在半导体衬底中埋入栅电极而形成，具有第一导电性的沟道的平面MOS晶体管和形成在栅极上的栅电极 半导体衬底和具有第二导电性沟道并具有形成在半导体衬底上的栅电极的平面MOS晶体管，所述半导体器件包括形成在垂直方向上方或上方的晶体管以外的其它电路元件 MOS晶体管具有第一导电类型的沟道。

公开(公告)号：US20060267015A1

公开(公告)日：2006-11-30

申请号：US11411119

申请日：2006-04-26

Applicant: Hiroshi Omi ,  Mamoru Furuta ,  Shoso Nambu ,  Takayoshi Dohi ,  Akihiro Takami ,  Shuji Manda ,  Hajime Inoue

Inventor： Hiroshi Omi ,  Mamoru Furuta ,  Shoso Nambu ,  Takayoshi Dohi ,  Akihiro Takami ,  Shuji Manda ,  Hajime Inoue

IPC: H01L29/04

CPC classification number: H01L29/4908 ,  H01L27/124 ,  H01L29/42384 ,  H01L29/66757 ,  H01L29/78675

Abstract: A gate electrode of a thin film transistor is composed by a three layer structure obtained by laminating a titanium nitride layer as an upper layer on an aluminum layer as a base layer and by laminating an unalloyed titanium layer as a lower layer under the base layer. An ion implantation is used as an ion doping into a source region and drain region as an active layer of the thin film transistor. The source region and the drain region are annealed at a low temperature of 350° C. to 450° C. to be activated. A chemical reaction between the base layer and the upper layer and between the base layer and the lower layer can be suppressed. The rise of the resistance value in the gate electrode can be suppressed. The resistance of the gate electrode can be reduced. The fluctuation of the threshold voltage of the thin film transistor can be suppressed.

Abstract translation: 薄膜晶体管的栅极由通过在作为基底层的铝层上层叠氮化钛层作为上层而获得的三层结构，并且在基底层下层叠作为下层的非合金化钛层而构成。 使用离子注入作为源极区和漏极区中的离子掺杂作为薄膜晶体管的有源层。 源极区域和漏极区域在350℃至450℃的低温下退火以被激活。 可以抑制基层与上层之间以及基层与下层之间的化学反应。 可以抑制栅电极中的电阻值的上升。 可以减小栅电极的电阻。 可以抑制薄膜晶体管的阈值电压的波动。

公开(公告)号：US08878263B2

公开(公告)日：2014-11-04

申请号：US12784639

申请日：2010-05-21

Applicant: Shuji Manda

Inventor： Shuji Manda

IPC: H01L31/0224 ,  H01L27/146 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/14609 ,  H01L27/14612 ,  H01L27/14645 ,  H01L27/14689 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7813

Abstract: Disclosed herein is a semiconductor device including: a semiconductor substrate; a gate insulating film formed on surfaces of the semiconductor substrate including an internal surface of a hole formed in the semiconductor substrate and formed by radical oxidation or plasma oxidation; and a gate electrode formed as buried in the hole. The gate insulating film and the gate electrode form a vertical MOS.

Abstract translation: 本发明公开了一种半导体器件，包括：半导体衬底; 形成在半导体衬底的表面上的栅极绝缘膜，包括形成在半导体衬底中并通过自由基氧化或等离子体氧化形成的孔的内表面; 以及形成为埋在孔中的栅电极。 栅极绝缘膜和栅电极形成垂直MOS。

公开(公告)号：US08212296B2

公开(公告)日：2012-07-03

申请号：US12778308

申请日：2010-05-12

Applicant: Shuji Manda ,  Hiroshi Takahashi

Inventor： Shuji Manda ,  Hiroshi Takahashi

IPC: H01L31/062

CPC classification number: H01L27/14603 ,  H01L21/823885 ,  H01L27/092 ,  H01L27/14609 ,  H01L27/14612 ,  H01L27/14632 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14689

Abstract: Disclosed herein is a semiconductor device having a vertical MOS transistor having a channel of a first conductivity type and formed by burying a gate electrode in a semiconductor substrate, a planar MOS transistor having a channel of the first conductivity and having a gate electrode formed on the semiconductor substrate, and a planar MOS transistor having a channel of a second conductivity and having a gate electrode formed on the semiconductor substrate, the semiconductor device, including other circuit element(s), other than a transistor, formed either below or above the vertical MOS transistor having the channel of the first conductivity type.

Abstract translation: 本发明公开了一种具有垂直MOS晶体管的半导体器件，其具有第一导电类型的沟道并且通过在半导体衬底中埋入栅电极而形成，具有第一导电性的沟道的平面MOS晶体管和形成在栅极上的栅电极 半导体衬底和具有第二导电性沟道并具有形成在半导体衬底上的栅电极的平面MOS晶体管，所述半导体器件包括形成在垂直方向上方或上方的晶体管以外的其它电路元件 MOS晶体管具有第一导电类型的沟道。

公开(公告)号：US20100314672A1

公开(公告)日：2010-12-16

申请号：US12784639

申请日：2010-05-21

Applicant: Shuji Manda

Inventor： Shuji Manda

IPC: H01L29/78 ,  H01L21/336 ,  H01L27/146

CPC classification number: H01L27/14609 ,  H01L27/14612 ,  H01L27/14645 ,  H01L27/14689 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7813

Abstract: Disclosed herein is a semiconductor device including: a semiconductor substrate; a gate insulating film formed on surfaces of the semiconductor substrate including an internal surface of a hole formed in the semiconductor substrate and formed by radical oxidation or plasma oxidation; and a gate electrode formed as buried in the hole. The gate insulating film and the gate electrode form a vertical MOS.

Abstract translation: 本发明公开了一种半导体器件，包括：半导体衬底; 形成在半导体衬底的表面上的栅极绝缘膜，包括形成在半导体衬底中并通过自由基氧化或等离子体氧化形成的孔的内表面; 以及形成为埋在孔中的栅电极。 栅极绝缘膜和栅电极形成垂直MOS。