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    Method of making II-VI semiconductor infrared light detector
    4.
    发明授权
    Method of making II-VI semiconductor infrared light detector 失效
    制备II-VI半导体红外光检测器的方法

    公开(公告)号：US5535699A

    公开(公告)日：1996-07-16

    申请号：US418886

    申请日：1995-04-07

    Applicant: Zempei Kawazu ,  Akihiro Takami

    Inventor： Zempei Kawazu ,  Akihiro Takami

    IPC: C30B19/04 ,  C30B29/46 ,  C30B33/02 ,  G01J1/02 ,  H01L21/368 ,  H01L31/0264 ,  H01L31/0296 ,  H01L31/10 ,  H01L31/103 ,  H01L31/18 ,  C30B25/04

    CPC classification number: H01L31/1832 ,  C30B19/04 ,  C30B29/48 ,  H01L21/02411 ,  H01L21/02562 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02625 ,  H01L21/02628 ,  H01L31/02963 ,  H01L31/1032 ,  H01L21/02557

    Abstract: A method for producing a photo-voltaic infrared detector including growing a crystalline CdHgTe layer on a CdTe substrate by liquid phase epitaxy using a growth melt including tellurium as a solvent to which indium is added as a dopant impurity in a concentration of from 0.01 to 0.1 ppm; annealing the CdHgTe layer to produce a p-type CdHgTe layer including indium as an n-type background dopant impurity; forming an n-type region of a desired depth as a light receiving region at the surface of the p-type CdHgTe layer by implanting a dopant impurity producing n-type conductivity and annealing; and forming an n-side electrode on the n-type region and a p-side electrode a prescribed distance from the n-type region on the p-type CdHgTe layer.

    Abstract translation: 一种光电红外检测器的制造方法，包括：使用包含碲作为掺杂铟作为掺杂剂的溶剂的生长熔液，通过液相外延在CdTe基板上生长结晶CdHgTe层，其浓度为0.01〜0.1 ppm; 退火CdHgTe层以产生包含铟作为n型背景掺杂剂杂质的p型CdHgTe层; 通过注入产生n型导电性和退火的掺杂剂杂质，在p型CdHgTe层的表面上形成具有所需深度的n型区域作为光接收区域; 在n型区域上形成n侧电极，在p型CdHgTe层上形成与n型区域规定距离的p侧电极。

    Zinc oxide varistor, a method of preparing the same, and a crystallized glass composition for coating
    5.
    发明授权
    Zinc oxide varistor, a method of preparing the same, and a crystallized glass composition for coating 失效
    氧化锌变阻器，其制备方法和用于涂布的结晶玻璃组合物

    公开(公告)号：US5294908A

    公开(公告)日：1994-03-15

    申请号：US689948

    申请日：1991-06-26

    Applicant: Masaaki Katsumata ,  Osamu Kanaya ,  Nobuharu Katsuki ,  Akihiro Takami

    Inventor： Masaaki Katsumata ,  Osamu Kanaya ,  Nobuharu Katsuki ,  Akihiro Takami

    IPC: H01C7/102 ,  H01C7/112 ,  H01C7/10

    CPC classification number: H01C7/102 ,  H01C7/112

    Abstract: The present invention relates to a zinc oxide varistor as a characteristic element of an arrestor for protecting a transmission and distribution line and peripheral devices thereof from surge voltage created by lightning, and more particularly a highly reliable zinc oxide varistor excellent in the non-linearity with respect to voltage, the discharge withstand current rating properties, and the life characteristics under voltage, a method of preparing the same, and PbO type crystallized glass for coating oxide ceramics employed for a zinc oxide varistor, etc. A zinc oxide varistor of the present invention includes a sintered body (1) and a high resistive side layer (3) consisting of crystallized glass with high crystallinity containing the prescribed amount of SiO.sub.2, MoO.sub.3, WO.sub.3, TiO.sub.2, NiO, etc., formed on the sides of the sintered body (1) to enhance the strength and the insulating property thereof, thereby improving the non-linearity with respect to voltage, the discharge withstand current rating properties and the life characteristics under voltage. The crystallized glass composition for coating of the present invention includes PbO as a main component and additives such as ZnO, B.sub.2 O.sub.3 , SiO.sub.2, MoO.sub.3, WO.sub.3, TiO.sub.2, and NiO to enhance the crystallinity and the insulating property thereof.

    Abstract translation: PCT No.PCT / JP90 / 01442 Sec。 371日期1991年6月26日 102（e）日期1991年6月26日PCT 1990年11月7日PCT PCT。 出版物WO91 / 07763 日本1991年5月30日。本发明涉及作为用于保护输配线及其外围装置的避雷器的特征元件的氧化锌压敏电阻与闪电产生的浪涌电压，更具体地说，涉及一种高可靠性的氧化锌压敏电阻 相对于电压的非线性，放电耐受电流等级特性，电压下的寿命特性，其制备方法，以及用于氧化锌变阻器等的氧化物陶瓷涂覆用PbO型结晶玻璃等。 本发明的氧化锌变阻器包括由含有规定量的SiO 2，MoO 3，WO 3，TiO 2，NiO等的具有高结晶度的结晶玻璃构成的烧结体（1）和高电阻侧层（3） 烧结体（1）的侧面增强其强度和绝缘性能，从而提高相对于电压的非线性，放电 Ge耐受额定电流特性和电压下的寿命特性。 本发明的涂布用结晶化玻璃组合物包括PbO作为主要成分，添加ZnO，B2O3，SiO2，MoO3，WO3，TiO2，NiO等添加剂，以提高其结晶性和绝缘性。

    Voltage-dependent non-linear resistance ceramic composition
    7.
    发明授权
    Voltage-dependent non-linear resistance ceramic composition 失效
    电压依赖非线性电阻陶瓷组成

    公开(公告)号：US4897219A

    公开(公告)日：1990-01-30

    申请号：US268618

    申请日：1988-11-07

    Applicant: Keiichi Noi ,  Akihiro Takami ,  Kazuhide Ebine ,  Kimiko Kumazawa

    Inventor： Keiichi Noi ,  Akihiro Takami ,  Kazuhide Ebine ,  Kimiko Kumazawa

    IPC: C04B35/47 ,  H01C7/115

    CPC classification number: H01C7/115 ,  C04B35/47

    Abstract: It is a voltage-dependent non-linear resistance ceramic composition comprising SrTiO.sub.3 as host material, Dy.sub.2 O.sub.3 or Dy.sub.2 O.sub.3 and Nb.sub.2 O.sub.5 or Ta.sub.2 O.sub.5 or Ta.sub.2 O.sub.5 and Nb.sub.2 O.sub.5 as accelerating agent for semiconductorization, thereby changing crystal to a low resistance, and changing crystal boundary to a high resistance.In case Dy.sub.2 O.sub.3 or Dy.sub.2 O.sub.3 and Nb.sub.2 O.sub.5 are used as the accelerating agent for semiconductorization, one kind or more selected from the group consisting of Na, K, Ca, Cd, In, Ba, Pb, Ag, Ce, La, Sc, Y, Cs, Au, Mg, Zr, Sn, Sb, W, Bi, Ni, Fe, Ga, Pt, Tl, Al, Si, Be, Li, Eu, Gd, Tb, Tm, Lu, Th, Ir, Os, Hf and Ru. Alternatively, in case Ta.sub.2 O.sub.5 or Ta.sub.2 O.sub.5 and Nb.sub.2 O.sub.5 are used as the accelerating agent for semiconductorization, one kind or more selected from the group consisting of Na, K, Ca, Cd, In, Ba, Pb, Mg, Zr, Sn, Sb, W, Bi, Eu, Gd, Tb, Tm, Lu, Th, Ir, Os, Hf, Ru, Ga, Pt, Tl, La, Sc, Y, Cs, and Au.As a result, baristor characteristic is obtainable by means of the high resistance at crystal boundaries and capacitor between crystal granules--crystal boundary--crystal granule.From this matter, an element having both functions of the baristor characteristics and the capacitor characteristics are obtainable, and performs effect in surge absorption and noise elimination.

    Abstract translation: 作为主要材料的SrTiO 3的电压依赖性非线性电阻陶瓷组合物，Dy 2 O 3，Dy 2 O 3，Nb 2 O 5，Ta 2 O 5，Ta 2 O 5，Nb 2 O 5等作为半导体用的加速剂，从而将晶体变为低电阻，将晶界改变为高 抵抗性。 在使用Dy2O3或Dy2O3和Nb2O5作为半导体加速剂的情况下，选自Na，K，Ca，Cd，In，Ba，Pb，Ag，Ce，La，Sc，Y， Cs，Au，Mg，Zr，Sn，Sb，W，Bi，Ni，Fe，Ga，Pt，Tl，Al，Si，Be，Li，Eu，Gd，Tb，Tm，Lu，Th，Ir， Hf和Ru。 或者，在使用Ta2O5或Ta2O5和Nb2O5作为半导体用加速剂的情况下，选自Na，K，Ca，Cd，In，Ba，Pb，Mg，Zr，Sn，Sb， W，Bi，Eu，Gd，Tb，Tm，Lu，Th，Ir，Os，Hf，Ru，Ga，Pt，Tl，La，Sc，Y，Cs和Au。 结果，可以通过晶界处的高电阻和晶粒之间的电容器 - 晶体边界晶粒颗粒获得电阻器特性。 由此，能够获得具有电阻特性和电容器特性两者的元件，并且能够实现浪涌吸收和噪声消除的效果。

    Photovoltaic device and manufacturing method thereof
    8.
    发明授权
    Photovoltaic device and manufacturing method thereof 有权
    光伏器件及其制造方法

    公开(公告)号：US08012787B2

    公开(公告)日：2011-09-06

    申请号：US12989098

    申请日：2008-04-30

    Applicant: Masato Yonezawa ,  Kimikazu Hazumi ,  Akihiro Takami ,  Hiroaki Morikawa ,  Kunihiko Nishimura

    Inventor： Masato Yonezawa ,  Kimikazu Hazumi ,  Akihiro Takami ,  Hiroaki Morikawa ,  Kunihiko Nishimura

    IPC: H01L21/00

    CPC classification number: H01L31/022425 ,  H01L31/0236 ,  H01L31/02363 ,  H01L31/03529 ,  H01L31/068 ,  Y02E10/547

    Abstract: The manufacturing method includes: forming a P-type silicon substrate and a high-concentration N-type diffusion layer, in which an N-type impurity is diffused in a first concentration, on an entire surface at a light-incident surface side; forming an etching resistance film on the high-concentration N-type diffusion layer and forming fine pores at a predetermined position within a recess forming regions on the etching resistance film; forming recesses by etching the silicon substrate around a forming position of the fine pores, so as not to leave the high-concentration N-type diffusion layer within the recess forming region; forming the low-concentration N-type diffusion layer, in which an N-type impurity is diffused in a second concentration that is lower than the first concentration, on a surface on which the recesses are formed; and forming a grid electrode in an electrode forming region at a light-incident surface side of the silicon substrate.

    Abstract translation: 该制造方法包括：在光入射表面侧的整个表面上形成P型硅衬底和其中N型杂质以第一浓度扩散的高浓度N型扩散层; 在高浓度N型扩散层上形成耐腐蚀性膜，在蚀刻电阻膜的凹部形成区域内的规定位置形成细孔; 通过在所述细孔的形成位置周围蚀刻所述硅基板而形成凹部，以便不将所述高浓度N型扩散层留在所述凹部形成区域内; 在其上形成凹部的表面上形成其中N型杂质以低于第一浓度的第二浓度扩散的低浓度N型扩散层; 以及在所述硅衬底的光入射表面侧的电极形成区域中形成栅电极。

    Method of fabricating a circuit array substrate
    9.
    发明授权
    Method of fabricating a circuit array substrate 有权
    制造电路阵列基板的方法

    公开(公告)号：US07564511B2

    公开(公告)日：2009-07-21

    申请号：US10968961

    申请日：2004-10-21

    Applicant: Hiroshi Tabatake ,  Tetsuya Kawamura ,  Shinichi Kawamura ,  Katsuhiko Inada ,  Atsushi Takeda ,  Nobuo Imai ,  Akihiro Takami

    Inventor： Hiroshi Tabatake ,  Tetsuya Kawamura ,  Shinichi Kawamura ,  Katsuhiko Inada ,  Atsushi Takeda ,  Nobuo Imai ,  Akihiro Takami

    IPC: G02F1/1333

    CPC classification number: G02F1/136204 ,  H01L27/12 ,  H01L27/124

    Abstract: A circuit array substrate includes an optically transparent substrate, pixels having switching elements formed on the transparent substrate, gate electrode lines connected to the switching elements, the gate electrode lines being provided on a first insulation film with separating portions in the pixels, signal lines connected to the switching elements, the signal lines being provided on a second insulation film which is different from the first insulation film, and electrically conductive portions provided on the second film to electrically connect the electrode lines with the separating portions to each other. The separating portions reduce electrostatic capacitances defined between the gate electrode lines and the switching elements when the conductive portions are not connected between the separating portions.

    Abstract translation: 电路阵列基板包括光学透明基板，具有形成在透明基板上的开关元件的像素，连接到开关元件的栅电极线，栅极电极线设置在具有像素中的分离部分的第一绝缘膜上，连接信号线 所述开关元件设置在与所述第一绝缘膜不同的第二绝缘膜上的所述信号线以及设置在所述第二膜上的导电部，以使所述电极线与所述分离部彼此电连接。 当导电部分未连接在分离部分之间时，分离部分减小限定在栅电极线和开关元件之间的静电电容。

    Thin film transistor, production method thereof and liquid crystal display device
    10.
    发明申请
    Thin film transistor, production method thereof and liquid crystal display device 审中-公开
    薄膜晶体管及其制造方法和液晶显示装置

    公开(公告)号：US20060267015A1

    公开(公告)日：2006-11-30

    申请号：US11411119

    申请日：2006-04-26

    Applicant: Hiroshi Omi ,  Mamoru Furuta ,  Shoso Nambu ,  Takayoshi Dohi ,  Akihiro Takami ,  Shuji Manda ,  Hajime Inoue

    Inventor： Hiroshi Omi ,  Mamoru Furuta ,  Shoso Nambu ,  Takayoshi Dohi ,  Akihiro Takami ,  Shuji Manda ,  Hajime Inoue

    IPC: H01L29/04

    CPC classification number: H01L29/4908 ,  H01L27/124 ,  H01L29/42384 ,  H01L29/66757 ,  H01L29/78675

    Abstract: A gate electrode of a thin film transistor is composed by a three layer structure obtained by laminating a titanium nitride layer as an upper layer on an aluminum layer as a base layer and by laminating an unalloyed titanium layer as a lower layer under the base layer. An ion implantation is used as an ion doping into a source region and drain region as an active layer of the thin film transistor. The source region and the drain region are annealed at a low temperature of 350° C. to 450° C. to be activated. A chemical reaction between the base layer and the upper layer and between the base layer and the lower layer can be suppressed. The rise of the resistance value in the gate electrode can be suppressed. The resistance of the gate electrode can be reduced. The fluctuation of the threshold voltage of the thin film transistor can be suppressed.

    Abstract translation: 薄膜晶体管的栅极由通过在作为基底层的铝层上层叠氮化钛层作为上层而获得的三层结构，并且在基底层下层叠作为下层的非合金化钛层而构成。 使用离子注入作为源极区和漏极区中的离子掺杂作为薄膜晶体管的有源层。 源极区域和漏极区域在350℃至450℃的低温下退火以被激活。 可以抑制基层与上层之间以及基层与下层之间的化学反应。 可以抑制栅电极中的电阻值的上升。 可以减小栅电极的电阻。 可以抑制薄膜晶体管的阈值电压的波动。

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