公开(公告)号：US20060267015A1

公开(公告)日：2006-11-30

申请号：US11411119

申请日：2006-04-26

申请人： Hiroshi Omi ,  Mamoru Furuta ,  Shoso Nambu ,  Takayoshi Dohi ,  Akihiro Takami ,  Shuji Manda ,  Hajime Inoue

发明人： Hiroshi Omi ,  Mamoru Furuta ,  Shoso Nambu ,  Takayoshi Dohi ,  Akihiro Takami ,  Shuji Manda ,  Hajime Inoue

IPC分类号： H01L29/04

CPC分类号： H01L29/4908 ,  H01L27/124 ,  H01L29/42384 ,  H01L29/66757 ,  H01L29/78675

摘要： A gate electrode of a thin film transistor is composed by a three layer structure obtained by laminating a titanium nitride layer as an upper layer on an aluminum layer as a base layer and by laminating an unalloyed titanium layer as a lower layer under the base layer. An ion implantation is used as an ion doping into a source region and drain region as an active layer of the thin film transistor. The source region and the drain region are annealed at a low temperature of 350° C. to 450° C. to be activated. A chemical reaction between the base layer and the upper layer and between the base layer and the lower layer can be suppressed. The rise of the resistance value in the gate electrode can be suppressed. The resistance of the gate electrode can be reduced. The fluctuation of the threshold voltage of the thin film transistor can be suppressed.

摘要翻译： 薄膜晶体管的栅极由通过在作为基底层的铝层上层叠氮化钛层作为上层而获得的三层结构，并且在基底层下层叠作为下层的非合金化钛层而构成。 使用离子注入作为源极区和漏极区中的离子掺杂作为薄膜晶体管的有源层。 源极区域和漏极区域在350℃至450℃的低温下退火以被激活。 可以抑制基层与上层之间以及基层与下层之间的化学反应。 可以抑制栅电极中的电阻值的上升。 可以减小栅电极的电阻。 可以抑制薄膜晶体管的阈值电压的波动。

公开(公告)号：US5888855A

公开(公告)日：1999-03-30

申请号：US572334

申请日：1995-12-14

申请人： Nobuya Nagahisa ,  Takaaki Kamimura ,  Kunio Matumura ,  Takayoshi Dohi

发明人： Nobuya Nagahisa ,  Takaaki Kamimura ,  Kunio Matumura ,  Takayoshi Dohi

IPC分类号： G02F1/136 ,  G02F1/1368 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/49 ,  H01L29/786

CPC分类号： H01L27/1214 ,  G02F1/1368 ,  H01L29/4908 ,  H01L29/78669 ,  H01L29/78696

摘要： The present invention has a semiconductor device including a substrate made of an insulating material, a gate electrode formed on the substrate, a thin film made of a silicon semiconductor and formed on the gate electrode through a gate insulating film, a protective film formed on the thin film and having two opposing major surfaces, and a source electrode and a drain electrode formed to be electrically connected with the thin film, wherein the first major surface of the two major surfaces of the protective film is in contact with the thin film, and a region near the second major surface of the protective film contains oxygen. The present invention has a method of manufacturing a semiconductor device, in which a gate electrode is on a substrate made of an insulating material, a thin film made of a silicon semiconductor is formed on the gate electrode through a gate insulating film, a protective film having two opposing major surfaces in which a first major surface is in contact with the thin film and a region near a second major surface contains oxygen is formed on the thin film, and a source electrode and a drain electrode are formed to electrically connect with the thin film.

摘要翻译： 本发明的半导体器件包括由绝缘材料制成的衬底，形成在衬底上的栅电极，由硅半导体制成的薄膜，并通过栅极绝缘膜形成在栅电极上，形成在保护膜上的保护膜 薄膜，具有两个相对的主表面，以及形成为与薄膜电连接的源电极和漏电极，其中保护膜的两个主表面的第一主表面与薄膜接触，以及 保护膜的第二主表面附近的区域含有氧。 本发明涉及一种半导体器件的制造方法，其中栅极位于由绝缘材料制成的衬底上，通过栅极绝缘膜在栅电极上形成由硅半导体制成的薄膜，保护膜 具有两个相对的主表面，其中第一主表面与薄膜接触，并且在薄膜上形成包含氧的第二主表面附近的区域，并且形成源电极和漏电极以与 薄膜。

公开(公告)号：US6146929A

公开(公告)日：2000-11-14

申请号：US347862

申请日：1999-07-09

申请人： Yasuhisa Oana ,  Kaichi Fukuda ,  Takayoshi Dohi

发明人： Yasuhisa Oana ,  Kaichi Fukuda ,  Takayoshi Dohi

IPC分类号： H01L29/786 ,  G02F1/136 ,  G02F1/1368 ,  H01L21/22 ,  H01L21/26 ,  H01L21/265 ,  H01L21/268 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L21/00

CPC分类号： H01L29/66757 ,  H01L27/1214 ,  H01L29/66765 ,  H01L29/78621 ,  Y10S438/909

摘要： In manufacturing a thin-film transistor on a glass substrate, a first thin film consisting of an amorphous silicon thin film is formed on the glass substrate, and a second thin film is formed on the first thin film. Then, this second thin film is etched to form a mask pattern. A dopant ion is doped into the first thin film through the mask pattern to form a source region and a drain region. The process of forming the mask pattern and the process of forming the source and drain regions are carried out continuously without exposing the substrate to the atmosphere.

摘要翻译： 在玻璃基板上制造薄膜晶体管时，在玻璃基板上形成由非晶硅薄膜构成的第一薄膜，在第一薄膜上形成第二薄膜。 然后，蚀刻该第二薄膜以形成掩模图案。 掺杂剂离子通过掩模图案掺杂到第一薄膜中以形成源极区和漏极区。 形成掩模图案的过程和形成源极和漏极区域的过程在不将基板暴露在大气中的情况下连续进行。

公开(公告)号：US06686287B1

公开(公告)日：2004-02-03

申请号：US09353661

申请日：1999-07-15

申请人： Takayoshi Dohi

发明人： Takayoshi Dohi

IPC分类号： H01L21302

CPC分类号： H01J37/321 ,  H01J37/32963 ,  H01L22/26

摘要： In patterning a silicon-containing thin film formed over an insulating substrate by means of vapor-phase chemical etching using a resist pattern formed on the thin film as a mask, a luminescence intensity A of wavelengths in a predetermined wavelength range and a luminescence intensity B at a specific wavelength are detected during the patterning. The luminescence intensity B is divided by the luminescence intensity A to produce a divide signal (B/A). The time of termination of the patterning is determined based on a change of the divide signal.

摘要翻译： 在通过使用形成在薄膜上的抗蚀剂图案作为掩模的气相化学蚀刻在绝缘基板上形成的含硅薄膜，在预定波长范围内的波长的发光强度A和发光强度B 在图案化期间检测特定波长。 将发光强度B除以发光强度A以产生除数信号（B / A）。 基于除数信号的变化来确定图案化终止的时间。

公开(公告)号：US06372083B1

公开(公告)日：2002-04-16

申请号：US09672447

申请日：2000-09-29

申请人： Yasuhisa Oana ,  Kaichi Fukuda ,  Takayoshi Dohi

发明人： Yasuhisa Oana ,  Kaichi Fukuda ,  Takayoshi Dohi

IPC分类号： H05H100

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L29/66757 ,  H01L29/66765 ,  H01L29/78621 ,  Y10S438/909

摘要： In manufacturing a thin-film transistor on a glass substrate, a first thin film consisting of an amorphous silicon thin film is formed on the glass substrate, and a second thin film is formed on the first thin film. Then, this second thin film is etched to form a mask pattern. A dopant ion is doped into the first thin film through the mask pattern to form a source region and a drain region. The process of forming the mask pattern and the process of forming the source and drain regions are carried out continuously without exposing the substrate to the atmosphere.

摘要翻译： 在玻璃基板上制造薄膜晶体管时，在玻璃基板上形成由非晶硅薄膜构成的第一薄膜，在第一薄膜上形成第二薄膜。 然后，蚀刻该第二薄膜以形成掩模图案。 掺杂剂离子通过掩模图案掺杂到第一薄膜中以形成源极区和漏极区。 形成掩模图案的过程和形成源极和漏极区域的过程在不将基板暴露在大气中的情况下连续进行。