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47 条记录 (耗时 0.043 秒)

    Telephone subscriber accomodation system in a broadband network
    1.
    发明授权
    Telephone subscriber accomodation system in a broadband network 失效
    宽带网络中的电话用户住宿系统

    公开(公告)号：US5521924A

    公开(公告)日：1996-05-28

    申请号：US384224

    申请日：1995-02-06

    申请人： Satoshi Kakuma ,  Shuji Yoshimura ,  Naoyuki Izawa

    发明人： Satoshi Kakuma ,  Shuji Yoshimura ,  Naoyuki Izawa

    IPC分类号： H04L29/06 ,  H04L12/66 ,  H04L12/951 ,  H04M3/00 ,  H04Q11/04 ,  H04J3/24

    CPC分类号： H04Q11/0478 ,  H04L2012/5614 ,  H04L2012/5672

    摘要： On receiving voice data from a subscriber accommodated in a broadband network, a terminal adaptor separately puts the voice data in cells in 8-bit units every 125 .mu.s separately, and transmits the cells by a remote switching unit in the broadband network to subscriber terminal equipment. The subscriber terminal equipment accommodates and processes each item of 8-bit data in 24 channels in the PCM format, puts in cells the PCM-formatted data in 24 channels, and sends the cells sequentially to a broadband network transmission line through the remote switching unit. On receiving the above described data in cells, an adaptor provided between the broadband network and an existing telephone network converts the data to the PCM transmission format, and sends them to the existing telephone network after adding a signaling bit to them.

    摘要翻译： 在从宽带网络中收到的用户接收语音数据的情况下，终端适配器分别将每个125μs的8位单元中的话音数据单独放置，并将宽带网络中的远程交换单元的小区发送给用户终端 设备。 用户终端设备以PCM格式适应和处理24个信道中的每个8位数据项，将PCM格式的数据单元格放入24个信道中，并通过远程交换单元将单元顺序发送到宽带网络传输线 。 在单元中接收上述数据之后，在宽带网络和现有电话网络之间提供的适配器将数据转换为PCM传输格式，并在向它们添加信令位之后将其发送到现有的电话网络。

    Apparatus for testing ATM channels
    2.
    发明授权
    Apparatus for testing ATM channels 失效
    ATM通道测试装置

    公开(公告)号：US5313453A

    公开(公告)日：1994-05-17

    申请号：US854888

    申请日：1992-03-20

    申请人： Yoshihiro Uchida ,  Satoshi Kakuma ,  Naoyuki Izawa ,  Yasuhiro Aso ,  Shuji Yoshimura ,  Masami Murayama

    发明人： Yoshihiro Uchida ,  Satoshi Kakuma ,  Naoyuki Izawa ,  Yasuhiro Aso ,  Shuji Yoshimura ,  Masami Murayama

    IPC分类号： H04L1/00 ,  H04L12/26 ,  H04L12/56 ,  H04Q11/04 ,  H04J3/14

    CPC分类号： H04L12/5601 ,  H04L1/0083 ,  H04L12/2697 ,  H04L43/50 ,  H04L49/1553 ,  H04L49/255 ,  H04L49/309 ,  H04Q11/0478 ,  H04J2203/0019 ,  H04L2012/5628 ,  H04L2012/5672 ,  H04L2012/5681

    摘要： A first form of an ATM channel testing apparatus tests an ATM channel by having a test cell detector in each switch to detect whether or not the switch appropriately switches a test cell generated by a test cell generating trunk. A second form of an ATM channel testing apparatus easily tests an ATM channel by having test cell generators provided for the respective input highways sequentially generating test cells including test cell identifying information and input highway identifying information, and having test cell checkers provided respectively for the output highways simply tally the test cells by the respective input highways. A third form of an ATM channel testing apparatus tests an ATM channel with less pieces of hardware by having turnaround parts in respective ordinary trunks sequentially turn around a test cell generated by a test cell generating trunk to be finally returned to the test cell generating trunk. A fourth form of an ATM channel testing apparatus tests an ATM channel by having a test cell checker provided for each of output highways to examine whether or not the test data carried in respective octets of the payloads in extracted test cells are of consecutive values.

    摘要翻译： ATM信道测试装置的第一形式通过在每个交换机中具有测试小区检测器来检测ATM信道，以检测交换机是否适当地切换由测试小区产生的中继线产生的测试小区。 ATM信道测试装置的第二种形式通过为相应的输入高速公路提供测试单元发生器来容易地测试ATM信道，该测试单元发生器依次产生包括测试单元识别信息和输入公路识别信息的测试单元，并且具有分别为输出提供的测试单元检查器 高速公路通过相应的输入高速公路简单地测试单元格。 ATM信道测试装置的第三种形式通过在相应的普通中继线中具有周转部分来顺序地转换由测试小区生成中继线产生的测试小区，以最终返回到测试小区生成中继线，来测试具有较少硬件的ATM信道。 ATM信道测试装置的第四种形式通过为每个输出高速公路提供测试单元检查来检测ATM信道，以检查提取的测试小区中有效载荷的相应八位字节中承载的测试数据是否是连续值。

    In-service activator for a broadband exchanger
    3.
    发明授权
    In-service activator for a broadband exchanger 失效
    宽带交换机的在线激活器

    公开(公告)号：US5295134A

    公开(公告)日：1994-03-15

    申请号：US853257

    申请日：1992-03-18

    申请人： Shuji Yoshimura ,  Satoshi Kakuma ,  Shiro Uriu ,  Naoyuki Izawa

    发明人： Shuji Yoshimura ,  Satoshi Kakuma ,  Shiro Uriu ,  Naoyuki Izawa

    IPC分类号： H04M3/22 ,  H04Q3/545 ,  H04Q11/04 ,  H04L12/26

    CPC分类号： H04L12/5601 ,  H04L49/106 ,  H04L49/255 ,  H04L49/3081 ,  H04L49/309 ,  H04Q11/0478 ,  H04L2012/5627 ,  H04L2012/5681

    摘要： An in-service activator for a broadband exchanger has a dual system structure, in which a first system and a second system form a dual pair. The first system and the second system in the dual pair each has at least one [1] channel converter and a switcher. A channel converter stores channel setting information for use in routing a cell inputted from a line, and outputs the cell inputted from the line by attaching the channel setting information to the cell. The switcher switches a cell outputted from a channel converter. The interfacer stores, in a channel converter of a to-be-activated standby system in the dual pair, the channel setting information read from the corresponding channel converter of an act system in the duplex pair.

    摘要翻译： 用于宽带交换机的在线激活器具有双系统结构，其中第一系统和第二系统形成双对。 双对中的第一系统和第二系统每个具有至少一个（1）信道转换器和切换器。 通道转换器存储用于路由从一行输入的单元的通道设置信息，并且通过将通道设置信息附加到该单元来输出从该行输入的单元。 切换器切换从信道转换器输出的单元。 该接口在双对中的待激活待机系统的信道转换器中存储从双工对中的动作系统的相应信道转换器读取的信道设置信息。

    Transmission test system in a broadband ISDN
    4.
    发明授权
    Transmission test system in a broadband ISDN 失效
    宽带ISDN中的传输测试系统

    公开(公告)号：US5251204A

    公开(公告)日：1993-10-05

    申请号：US762338

    申请日：1991-09-19

    申请人： Naoyuki Izawa ,  Shuji Yoshimura ,  Satoshi Kakuma

    发明人： Naoyuki Izawa ,  Shuji Yoshimura ,  Satoshi Kakuma

    IPC分类号： H04J3/14 ,  H04J3/16 ,  H04L12/70 ,  H04Q11/04

    CPC分类号： H04Q11/0478 ,  H04J3/14 ,  H04J3/1617 ,  H04J2203/0089 ,  H04L2012/5628 ,  H04L2012/5672

    摘要： The present invention relates to a transmission line test method in the broadband ISDN for assembling an ATM formatted cell into a frame and sending it in the synchronous optical network (SONET) formatted transmission line as a protocol of an optical fiber communication network. First, test data are inserted into an ATM cell according to a command of the central controlling unit in an ATM switching unit. Then, the test cell is sent through an ATM switch in the ATM switching unit after the insertion of the test data; the test data are extracted from the test cell turned around by an ATM layer provided between the ATM switch and the SONET-formatted transmission line or by a subscriber terminal adapter, or from the test frame (including the test cell) turned around by a terminator in the SONET-formatted transmission line or by a network terminator at a subscriber terminal in the transmission line; and finally a transmission test is conducted by checking the data in the line up to each turnaround point.

    摘要翻译： 本发明涉及宽带ISDN中用于将ATM格式化小区组装成帧并在作为光纤通信网络的协议的同步光网络（SONET）格式化传输线路中发送它的传输线路测试方法。 首先，根据ATM交换单元中的中央控制单元的命令将测试数据插入到ATM信元中。 然后，测试单元在插入测试数据之后通过ATM交换单元中的ATM交换机发送; 从由ATM交换机和SONET格式的传输线之间提供的ATM层或由用户终端适配器或由终端器转过的测试框（包括测试单元）转移的测试单元提取测试数据 在SONET格式的传输线路中，或者由传输线路中的用户终端的网络终端器; 最后通过检查直到每个周转点的行中的数据进行传输测试。

    Elastic store memory circuit
    6.
    发明授权
    Elastic store memory circuit 失效
    弹性存储器电路

    公开(公告)号：US5444658A

    公开(公告)日：1995-08-22

    申请号：US206221

    申请日：1994-03-07

    申请人： Naoyuki Izawa ,  Yasuhiro Aso ,  Yoshihiro Uchida ,  Satoshi Kakuma

    发明人： Naoyuki Izawa ,  Yasuhiro Aso ,  Yoshihiro Uchida ,  Satoshi Kakuma

    IPC分类号： H04J3/06 ,  H04L7/00 ,  G11C7/00

    CPC分类号： H04J3/0626

    摘要： An elastic store memory circuit includes first and second elastic store memories. Each of the first and second elastic store memories generates a phase comparison signal when a phase difference between a write timing and a read timing is within a predetermined phase range. The elastic store memory circuit also includes a selector which selects either the input data read out from the first elastic store memory or the input data read out from the second elastic store memory, and a slip signal generator for generating a slip signal on the basis of a write reset timing at which the first and second elastic store memories are reset, a read reset timing at which the first and second elastic store memories are reset, and the phase comparison signal. The slip signal indicates which one of the write reset timing and the read reset timing precedes the other one.

    摘要翻译： 弹性存储存储器电路包括第一和第二弹性存储器存储器。 当写入定时和读取定时之间的相位差在预定相位范围内时，第一和第二弹性存储存储器中的每一个产生相位比较信号。 弹性存储器电路还包括选择器，其选择从第一弹性存储存储器读出的输入数据或从第二弹性存储器读出的输入数据，以及滑移信号发生器，用于基于 复位第一和第二弹性存储器的写入复位定时，复位第一和第二弹性存储器的读取复位定时以及相位比较信号。 打印信号指示写入复位定时和读取复位定时中哪一个先于另一个。

    Address decision system having address check system
    8.
    发明授权
    Address decision system having address check system 失效
    具有地址检查系统的地址决策系统

    公开(公告)号：US5459743A

    公开(公告)日：1995-10-17

    申请号：US275306

    申请日：1994-07-15

    申请人： Naoki Fukuda ,  Shuji Yoshimura ,  Satoshi Kakuma

    发明人： Naoki Fukuda ,  Shuji Yoshimura ,  Satoshi Kakuma

    IPC分类号： H04M11/00 ,  H04L12/28 ,  H04L12/70 ,  H04L12/56

    CPC分类号： H04L49/309 ,  H04L49/3009 ,  H04L49/3081 ,  H04L49/555 ,  H04L2012/5627 ,  H04L49/30 ,  H04L49/503

    摘要： In an address decision system in an ATM exchange, a table memory stores data showing relationships between VPI/VCI values and addresses. A latch circuit latches a VPI/VCI value contained in a cell transferred via a cell highway. A comparator circuit compares the VPI/VCI values stored in the table memory with the VPI/VCI value latched by the latch and generates a comparator output signal showing, in a normal operation, one of the addresses at which the VPI/VCI value from the latch circuit coincides with one of the VPI/VCI values in the table memory. An address decision unit encodes the comparator output signal and generates an encoded signal based on the comparator output signal. A decoder unit decodes the encoded signal and generates a decoded signal. A check unit receives the comparator output signal and the encoded signal and generates an error signal when the comparator output signal and the encoded signal do not match each other.

    摘要翻译： 在ATM交换机的地址决定系统中，表存储器存储表示VPI / VCI值与地址之间的关系的数据。 锁存电路锁存通过单元高速公路传送的单元中包含的VPI / VCI值。 比较器电路将存储在表存储器中的VPI / VCI值与由锁存器锁存的VPI / VCI值进行比较，并产生比较器输出信号，该信号表示在正常操作中VPI / VCI值来自 锁存电路与表存储器中的一个VPI / VCI值一致。 地址决定单元对比较器输出信号进行编码，并根据比较器输出信号产生编码信号。 解码器单元解码编码信号并产生解码信号。 检查单元接收比较器输出信号和编码信号，并且当比较器输出信号和编码信号彼此不匹配时产生误差信号。

    Signaling data receiving and processing unit provided in a broadband integrated services digital network
    10.
    发明授权
    Signaling data receiving and processing unit provided in a broadband integrated services digital network 失效
    在宽带综合业务数字网络中提供的信令数据接收和处理单元

    公开(公告)号：US5369649A

    公开(公告)日：1994-11-29

    申请号：US731332

    申请日：1991-07-17

    申请人： Masami Murayama ,  Satoshi Kakuma ,  Shuji Yoshimura

    发明人： Masami Murayama ,  Satoshi Kakuma ,  Shuji Yoshimura

    IPC分类号： H04L1/00 ,  H04L12/951 ,  H04M7/00 ,  H04Q11/04 ,  G06F11/10

    CPC分类号： H04Q11/0478 ,  H04L2012/563

    摘要： An error check of a signaling data divided into divided signaling data transferred asynchronously in a unit of cells is performed in a signaling data receiving and processing unit in a digital exchange. The exchange is connected with terminal equipment arranged in a narrow band ISDN environment in a broadband ISDN system. The error check is performed by calculating an error check code for every byte of the signaling data as it is received, accumulating the result until the cyclic redundancy code, encountered in the last byte of the signaling data, is accumulated and performing matching between the accumulated result and a constant value produced based on the CRC system. The checking is performed while the signaling data is stored in a data memory in the signaling data receiving and processing unit. The data memory provided in the signaling data receiving and processing unit has memory regions capable of storing the signaling data sent from the terminal which is allocated as needed by a central controller of the digital exchange.

    摘要翻译： 在数字交换中的信令数据接收和处理单元中执行分组为以小区为单位异步传送的分离信令数据的信令数据的错误检查。 该交换机与宽带ISDN系统中布置在窄带ISDN环境中的终端设备连接。 通过计算接收到的信令数据的每个字节的错误校验码来进行错误检查，累加结果，直到在信令数据的最后一个字节中遇到的循环冗余码被累积并执行累积的 结果和基于CRC系统产生的恒定值。 当信令数据存储在信令数据接收和处理单元中的数据存储器中时，执行检查。 提供在信令数据接收和处理单元中的数据存储器具有能够存储从数字交换机的中央控制器根据需要分配的从终端发送的信令数据的存储区域。