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公开(公告)号：US09041006B2
公开(公告)日：2015-05-26
申请号：US12409964
申请日：2009-03-24
IPC分类号： H01L29/15 , H01L29/66 , H01L21/04 , H01L29/08 , H01L29/78 , H01L29/861 , H01L29/06 , H01L29/16 , H01L29/423
CPC分类号： H01L29/7813 , H01L21/046 , H01L29/0623 , H01L29/086 , H01L29/0878 , H01L29/1608 , H01L29/4236 , H01L29/42368 , H01L29/6606 , H01L29/66068 , H01L29/8613
摘要： A silicon carbide MOS semiconductor device is disclosed which suppresses degradation of efficiency percentage yield with respect to a breakdown voltage even when a surface region with a high impurity concentration is formed by ion implantation with such a high dose as required for attaining a good ohmic contact. The device has a silicon carbide semiconductor substrate, a voltage blocking layer of a first conductivity type formed on the substrate, a body region of a second conductivity type formed on the voltage blocking layer, a body contact region of the second conductivity type formed in a surface region of the body region by selective ion implantation, a surface of the body contact region having such a high impurity concentration as to impart an ohmic contact, a source contact region of the first conductivity type formed in a surface region of the body region by selective ion implantation, a surface of the source contact region having such a high impurity concentration as to impart an ohmic contact, and a source extension region with an impurity concentration lower than that in the source contact region under the source contact region at a region deeper than a tail part of a bottom region of the source contact region by selective ion implantation, the source extension region having an impurity concentration less than 3×1019 cm−3.
摘要翻译： 公开了一种碳化硅MOS半导体器件，其即使当通过以达到良好的欧姆接触所需的高剂量的离子注入形成具有高杂质浓度的表面区域时，也可以相对于击穿电压降低效率百分比。 该器件具有碳化硅半导体衬底，形成在衬底上的第一导电类型的电压阻挡层，形成在电压阻挡层上的第二导电类型的体区，形成在第二导电类型的体接触区 通过选择性离子注入，体区域的表面区域，具有如此高的杂质浓度以产生欧姆接触的体接触区域的表面，在身体区域的表面区域中形成的第一导电类型的源极接触区域由 选择性离子注入，源极接触区域的表面具有如此高的杂质浓度以施加欧姆接触，以及源极延伸区域，其源极延伸区域的杂质浓度低于在源极接触区域下的源极接触区域中的杂质浓度 比源极接触区域的底部区域的尾部通过选择性离子注入，源极延伸区域具有杂质 浓度小于3×1019 cm-3。
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2.发明授权公开(公告)号：US08406024B2
公开(公告)日：2013-03-26
申请号：US12662595
申请日：2010-04-26
申请人： Shun-ichi Nakamura
发明人： Shun-ichi Nakamura
IPC分类号： H02M7/537
摘要： A power conversion circuit converting DC electric power into AC electric power and sending the AC power to an inductive load, includes a first switching device connected to the positive pole side of the DC power supply to exhibit a conductive state and an interrupted state of a current; a second switching device connected to the negative pole side of the DC power supply to exhibit a conductive state and an interrupted state of the current; a first inductor provided between the first switching device and the inductive load; a second inductor provided between the second switching device and the inductive load; and a clamping diode connected between a first connection point between the first switching device and the first inductor, and a second connection point between the second switching device and the second inductor. Thus, conduction is provided from the second connection point to the first connection point.
摘要翻译： 将直流电转换为交流电并将交流电力发送到感性负载的电力转换电路包括连接到直流电源的正极侧的第一开关装置，以呈现导通状态和电流的中断状态 ; 连接到直流电源的负极侧的第二开关器件呈现导通状态和电流的中断状态; 设置在所述第一开关器件和所述电感负载之间的第一电感器; 设置在所述第二开关装置和所述感性负载之间的第二电感器; 以及连接在第一开关器件和第一电感器之间的第一连接点与第二开关器件与第二电感器之间的第二连接点的钳位二极管。 因此，从第二连接点向第一连接点提供导通。
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公开(公告)号：US20090236612A1
公开(公告)日：2009-09-24
申请号：US12409964
申请日：2009-03-24
IPC分类号： H01L29/161
CPC分类号： H01L29/7813 , H01L21/046 , H01L29/0623 , H01L29/086 , H01L29/0878 , H01L29/1608 , H01L29/4236 , H01L29/42368 , H01L29/6606 , H01L29/66068 , H01L29/8613
摘要： A silicon carbide MOS semiconductor device is disclosed which suppresses degradation of efficiency percentage yield with respect to a breakdown voltage even when a surface region with a high impurity concentration is formed by ion implantation with such a high dose as required for attaining a good ohmic contact. The device has a silicon carbide semiconductor substrate, a voltage blocking layer of a first conductivity type formed on the substrate, a body region of a second conductivity type formed on the voltage blocking layer, a body contact region of the second conductivity type formed in a surface region of the body region by selective ion implantation, a surface of the body contact region having such a high impurity concentration as to impart an ohmic contact, a source contact region of the first conductivity type formed in a surface region of the body region by selective ion implantation, a surface of the source contact region having such a high impurity concentration as to impart an ohmic contact, and a source extension region with an impurity concentration lower than that in the source contact region under the source contact region at a region deeper than a tail part of a bottom region of the source contact region by selective ion implantation, the source extension region having an impurity concentration less than 3×1019 cm−3.
摘要翻译： 公开了一种碳化硅MOS半导体器件，其即使当通过以达到良好的欧姆接触所需的高剂量的离子注入形成具有高杂质浓度的表面区域时，也可以相对于击穿电压降低效率百分比。 该器件具有碳化硅半导体衬底，形成在衬底上的第一导电类型的电压阻挡层，形成在电压阻挡层上的第二导电类型的体区，形成在第二导电类型的体接触区 通过选择性离子注入，体区域的表面区域，具有如此高的杂质浓度以产生欧姆接触的体接触区域的表面，在身体区域的表面区域中形成的第一导电类型的源极接触区域由 选择性离子注入，源极接触区域的表面具有如此高的杂质浓度以施加欧姆接触，以及源极延伸区域，其源极延伸区域的杂质浓度低于在源极接触区域下的源极接触区域中的杂质浓度 比源极接触区域的底部区域的尾部通过选择性离子注入，源极延伸区域具有杂质 浓度小于3×1019 cm-3。
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公开(公告)号：US20070057262A1
公开(公告)日：2007-03-15
申请号：US11530850
申请日：2006-09-11
IPC分类号： H01L31/0312
CPC分类号： H01L29/7813 , H01L21/046 , H01L29/045 , H01L29/0878 , H01L29/1608 , H01L29/4236 , H01L29/66068 , Y10S438/931
摘要： In a semiconductor device having SiC vertical trench MOSFETs, it is aimed to prevent the generation of large scattering in the channel resistance without largely increasing the average value of channel resistance. A 4H-SiC substrate having a major face thereof that is generally a {0001} face and having an off angle α. The trench is formed with the standard deviation σ in scattering of the angle formed by a trench side wall face and a substrate major face within a wafer face. By setting the designed value of the angle formed by the trench side wall face and the substrate major face at an any angle ranging from [(60 degrees)+2σ] to [(90 degrees)−tan−1 (0.87×tan α)−2σ] in forming the trench in the SiC substrate, a semiconductor device in which the angle formed by the trench side wall face and the substrate major face is 60 degrees or more but not more than [(90 degrees)−tan−1 (0.87×tan α)] can be obtained.
摘要翻译： 在具有SiC垂直沟槽MOSFET的半导体器件中，旨在防止在沟道电阻中产生大的散射，而不会大大增加沟道电阻的平均值。 具有主面的4H-SiC衬底通常为{0001}面并具有偏角α。 沟槽由晶片面内的沟槽侧壁面和基板主面所形成的角度的散射形成有标准偏差σ。 通过将沟槽侧壁面和基板主面形成的角度的设计值设定为从[（60度）+2σ]到[（90度）-1“-1”的任意角度 在形成SiC衬底中的沟槽的情况下，形成沟槽（...）的半导体器件，其中由沟槽侧壁面和衬底主面形成的角度为60度以上但不大于[（90度） ）-ATAN-1（0.87葡萄糖α）]。
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5.发明授权Silicon carbide semiconductor element, method of manufacturing the same, and silicon carbide device 有权碳化硅半导体元件及其制造方法以及碳化硅器件公开(公告)号：US08114783B2
公开(公告)日：2012-02-14
申请号：US12193291
申请日：2008-08-18
IPC分类号： H01L31/0312
CPC分类号： H01L21/0485 , H01L29/1608 , H01L29/66068
摘要： A silicon carbide semiconductor element and a manufacturing method thereof are disclosed in which a low contact resistance is attained between an electrode film and a wiring conductor element, and the wiring conductor element is hardly detached from the electrode film. In the method, a nickel film and a nickel oxide film are laminated in this order on a surface of an n-type silicon carbide substrate or an n-type silicon carbide region of a silicon carbide substrate, followed by a heat treatment under a non-oxidizing condition. The heat treatment transforms a portion of the nickel film into a nickel silicide film. Then, the nickel oxide film is removed with hydrochloric acid solution, and subsequently, a nickel aluminum film and an aluminum film are laminated in this order on a surface of the nickel silicide film.
摘要翻译： 公开了一种碳化硅半导体元件及其制造方法，其中在电极膜和布线导体元件之间获得低接触电阻，并且布线导体元件几乎不与电极膜分离。 在该方法中，将镍膜和氧化镍膜依次层叠在碳化硅基板的n型碳化硅基板或n型碳化硅区域的表面上，然后在非碳化硅基板 氧化条件。 热处理将镍膜的一部分转变成硅化镍膜。 然后，用盐酸溶液除去氧化镍膜，然后依次将镍铝膜和铝膜层叠在硅化镍膜的表面上。
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6.发明授权Silicon carbide semiconductor element, method of manufacturing the same, and silicon carbide device 有权碳化硅半导体元件及其制造方法以及碳化硅器件公开(公告)号：US09117681B2
公开(公告)日：2015-08-25
申请号：US13346864
申请日：2012-01-10
CPC分类号： H01L21/0485 , H01L29/1608 , H01L29/66068
摘要： A silicon carbide semiconductor element and a manufacturing method thereof are disclosed in which a low contact resistance is attained between an electrode film and a wiring conductor element, and the wiring conductor element is hardly detached from the electrode film. In the method, a nickel film and a nickel oxide film are laminated in this order on a surface of an n-type silicon carbide substrate or an n-type silicon carbide region of a silicon carbide substrate, followed by a heat treatment under a non-oxidizing condition. The heat treatment transforms a portion of the nickel film into a nickel silicide film. Then, the nickel oxide film is removed with hydrochloric acid solution, and subsequently, a nickel aluminum film and an aluminum film are laminated in this order on a surface of the nickel silicide film.
摘要翻译： 公开了一种碳化硅半导体元件及其制造方法，其中在电极膜和布线导体元件之间获得低接触电阻，并且布线导体元件几乎不与电极膜分离。 在该方法中，将镍膜和氧化镍膜依次层叠在碳化硅基板的n型碳化硅基板或n型碳化硅区域的表面上，然后在非碳化硅基板 氧化条件。 热处理将镍膜的一部分转变成硅化镍膜。 然后，用盐酸溶液除去氧化镍膜，然后依次将镍铝膜和铝膜层叠在硅化镍膜的表面上。
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7.发明申请公开(公告)号：US20130176760A1
公开(公告)日：2013-07-11
申请号：US13783860
申请日：2013-03-04
申请人： Shun-ichi NAKAMURA
发明人： Shun-ichi NAKAMURA
IPC分类号： H02M7/537
摘要： A power conversion circuit converting DC electric power into AC electric power and sending the AC power to an inductive load, includes a first switching device connected to the DC power supply; a second switching device connected to the DC power supply; a first inductor provided between the first switching device and the inductive load; a second inductor provided between the second switching device and the inductive load; and a clamping diode connected between a first connection point between the first switching device and the first inductor, and a second connection point between the second switching device and the second inductor. When the first and second switching devices are turned off, a current flows through the second diode, clamping diode, first inductor and inductive load to completely flow out a current in the first inductor, and then a current flows through the second diode, second inductor and inductive load.
摘要翻译： 将直流电转换为交流电力并将交流电力发送到电感性负载的电力转换电路包括连接到直流电源的第一开关装置; 连接到所述直流电源的第二开关装置; 设置在所述第一开关器件和所述电感负载之间的第一电感器; 设置在所述第二开关装置和所述感性负载之间的第二电感器; 以及连接在第一开关器件和第一电感器之间的第一连接点与第二开关器件与第二电感器之间的第二连接点的钳位二极管。 当第一和第二开关器件关断时，电流流过第二二极管，钳位二极管，第一电感器和感性负载，以完全流出第一电感器中的电流，然后电流流过第二二极管，第二电感器 和感性负载。
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公开(公告)号：US20100019250A1
公开(公告)日：2010-01-28
申请号：US12574805
申请日：2009-10-07
CPC分类号： H01L29/7813 , H01L29/0619 , H01L29/0649 , H01L29/0657 , H01L29/0661 , H01L29/0878 , H01L29/1608 , H01L29/4236 , H01L29/42368 , H01L29/4238 , H01L29/66068 , H01L29/7811
摘要： A semiconductor device and a method of forming thereof has a base body has a field stopping layer, a drift layer, a current spreading layer, a body region, and a source contact region layered in the order on a substrate. A trench that reaches the field stopping layer or the substrate is provided. A gate electrode is provided in the upper half section in the trench. In a section deeper than the position of the gate electrode in the trench, an insulator is buried that has a normal value of insulation breakdown electric field strength equal to or greater than the value of the insulation breakdown electric field strength of the semiconductor material of the base body. This inhibits short circuit between a gate and a drain due to insulation breakdown of an insulator film at the bottom of the trench to realize a high breakdown voltage in a semiconductor device using a semiconductor material such as SiC. The sidewall surfaces of the trench located below the gate electrode is inclined to form a trapezoidal profile.
摘要翻译： 半导体器件及其形成方法具有在基板上依次层叠的场阻挡层，漂移层，电流扩展层，体区域和源极接触区域。 提供到达场停止层或基板的沟槽。 栅极电极设置在沟槽中的上半部分中。 在比沟槽中的栅电极的位置更深的部分中，埋入绝缘体的绝缘击穿电场强度的正常值等于或大于绝缘击穿电场强度的绝缘击穿电场强度 基体 由于沟槽底部的绝缘体膜的绝缘击穿，这就抑制了栅极和漏极之间的短路，从而在使用诸如SiC的半导体材料的半导体器件中实现高的击穿电压。 位于栅电极下方的沟槽的侧壁表面倾斜以形成梯形轮廓。
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公开(公告)号：US08178920B2
公开(公告)日：2012-05-15
申请号：US12574805
申请日：2009-10-07
IPC分类号： H01L29/76
CPC分类号： H01L29/7813 , H01L29/0619 , H01L29/0649 , H01L29/0657 , H01L29/0661 , H01L29/0878 , H01L29/1608 , H01L29/4236 , H01L29/42368 , H01L29/4238 , H01L29/66068 , H01L29/7811
摘要： A semiconductor device and a method of forming thereof has a base body has a field stopping layer, a drift layer, a current spreading layer, a body region, and a source contact region layered in the order on a substrate. A trench that reaches the field stopping layer or the substrate is provided. A gate electrode is provided in the upper half section in the trench. In a section deeper than the position of the gate electrode in the trench, an insulator is buried that has a normal value of insulation breakdown electric field strength equal to or greater than the value of the insulation breakdown electric field strength of the semiconductor material of the base body. This inhibits short circuit between a gate and a drain due to insulation breakdown of an insulator film at the bottom of the trench to realize a high breakdown voltage in a semiconductor device using a semiconductor material such as SiC. The sidewall surfaces of the trench located below the gate electrode is inclined to form a trapezoidal profile.
摘要翻译： 半导体器件及其形成方法具有在基板上依次层叠的场阻挡层，漂移层，电流扩展层，体区域和源极接触区域。 提供到达场停止层或基板的沟槽。 栅极电极设置在沟槽中的上半部分中。 在比沟槽中的栅电极的位置更深的部分中，埋入绝缘体的绝缘击穿电场强度的正常值等于或大于绝缘击穿电场强度的绝缘击穿电场强度 基体 由于沟槽底部的绝缘体膜的绝缘击穿，这就抑制了栅极和漏极之间的短路，从而在使用诸如SiC的半导体材料的半导体器件中实现高的击穿电压。 位于栅电极下方的沟槽的侧壁表面倾斜以形成梯形轮廓。
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10.发明申请SILICON CARBIDE SEMICONDUCTOR ELEMENT, METHOD OF MANUFACTURING THE SAME, AND SILICON CARBIDE DEVICE 有权硅碳化硅半导体元件及其制造方法和碳化硅器件公开(公告)号：US20120104417A1
公开(公告)日：2012-05-03
申请号：US13346864
申请日：2012-01-10
IPC分类号： H01L29/24
CPC分类号： H01L21/0485 , H01L29/1608 , H01L29/66068
摘要： A silicon carbide semiconductor element and a manufacturing method thereof are disclosed in which a low contact resistance is attained between an electrode film and a wiring conductor element, and the wiring conductor element is hardly detached from the electrode film. In the method, a nickel film and a nickel oxide film are laminated in this order on a surface of an n-type silicon carbide substrate or an n-type silicon carbide region of a silicon carbide substrate, followed by a heat treatment under a non-oxidizing condition. The heat treatment transforms a portion of the nickel film into a nickel silicide film. Then, the nickel oxide film is removed with hydrochloric acid solution, and subsequently, a nickel aluminum film and an aluminum film are laminated in this order on a surface of the nickel silicide film.
摘要翻译： 公开了一种碳化硅半导体元件及其制造方法，其中在电极膜和布线导体元件之间获得低接触电阻，并且布线导体元件几乎不与电极膜分离。 在该方法中，将镍膜和氧化镍膜依次层叠在碳化硅基板的n型碳化硅基板或n型碳化硅区域的表面上，然后在非碳化硅基板 氧化条件。 热处理将镍膜的一部分转变成硅化镍膜。 然后，用盐酸溶液除去氧化镍膜，然后依次将镍铝膜和铝膜层叠在硅化镍膜的表面上。
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