公开(公告)号：US5173439A

公开(公告)日：1992-12-22

申请号：US679568

申请日：1991-04-02

申请人： Somanath Dash ,  Michael L. Kerbaugh ,  Charles W. Koburger, III ,  Brian J. Machesney ,  Nitin B. Parekh

发明人： Somanath Dash ,  Michael L. Kerbaugh ,  Charles W. Koburger, III ,  Brian J. Machesney ,  Nitin B. Parekh

IPC分类号： H01L21/3105 ,  H01L21/311 ,  H01L21/762

CPC分类号： H01L21/02063 ,  H01L21/3105 ,  H01L21/31053 ,  H01L21/31116 ,  H01L21/76229

摘要： A method of forming a planarized dielectric filled wide shallow trench in a semi-conductor substrate is provided. A layer of etch stop such as Si.sub.3 N.sub.4 is deposited onto the semi-conductor substrate, and wide trenches are formed through the Si.sub.3 N.sub.4 into the substrate by conventional RIE. The surface of the substrate including the trenches have formed thereon a SiO.sub.2 coating, conforming to the surface of the substrate. A layer of etch resistant material such as polysilicon is deposited onto the SiO.sub.2 material. The polysilicon outside the width of the trenches is then removed by chemical-mechanical polishing to expose the SiO.sub.2 there below, while leaving the SiO.sub.2 above the trenches covered with polysilicon. The exposed SiO.sub.2 is then RIE etched down to the Si.sub.3 N.sub.4, leaving a plug of SiO.sub.2 capped with the etch resistant polysilicon over each trench. These plugs are then removed by mechanical polishing down to the Si.sub.3 N.sub.4, to provide a planarized upper surface of SiO.sub.2 and Si.sub.3 N.sub.4 on the top of the substrate. The invention also is useful in forming planarized surfaces on substrates having trenches filled with conductive material.

摘要翻译： 提供了一种在半导体衬底中形成平坦化介质填充的宽浅沟槽的方法。 将诸如Si 3 N 4的蚀刻停止层沉积到半导体衬底上，并且通过常规RIE通过Si 3 N 4形成宽的沟槽进入衬底。 包括沟槽的衬底的表面在其上形成符合衬底表面的SiO 2涂层。 将诸如多晶硅的耐蚀刻材料层沉积到SiO 2材料上。 然后通过化学机械抛光去除沟槽宽度外的多晶硅，以在下面暴露出SiO 2，同时在覆盖有多晶硅的沟槽上留下SiO 2。 然后将暴露的SiO 2 RIE蚀刻到Si 3 N 4上，在每个沟槽上留下带有耐蚀刻多晶硅的SiO 2塞。 然后通过机械抛光除去Si 3 N 4，从而在衬底的顶部提供SiO 2和Si 3 N 4的平坦化上表面。 本发明还可用于在具有填充有导电材料的沟槽的衬底上形成平坦化表面。

公开(公告)号：US4399605A

公开(公告)日：1983-08-23

申请号：US352990

申请日：1982-02-26

申请人： Somanath Dash ,  Richard R. Garnache ,  Ronald R. Troutman

发明人： Somanath Dash ,  Richard R. Garnache ,  Ronald R. Troutman

IPC分类号： H01L29/80 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H01L21/265 ,  H01L21/28

CPC分类号： H01L21/823842 ,  H01L29/4908 ,  H01L29/4975 ,  H01L27/12

摘要： A method is provided for making complementary field effect transistors in a semiconductor layer having a first portion including an N type transistor with a channel region defined by N+ source and drain regions and having a second portion including a P type transistor with a channel region defined by P+ source and drain regions. An insulating layer is disposed over the first and second portions with thin insulating films formed over the channel regions. The steps of the method include applying a masking layer over the insulating layer having an opening over one of the portions, introducing a first impurity into the channel region of the one portion for channel tailoring purposes, depositing a first conductive refractory material on the thin insulating film located over the channel region of the one portion, removing the masking layer, introducing a second impurity into the channel region of the other portion for channel tailoring purposes and depositing a second conductive material on the thin insulating film located over the channel region of the other portion and in contact with the first conductive material. The first and second conductive materials have different work functions. The first conductive material is, preferably, platinum silicide while the second conductive material may be aluminum.

摘要翻译： 提供了一种在半导体层中制造互补场效应晶体管的方法，该半导体层具有第一部分，该第一部分包括具有由N +源极和漏极区限定的沟道区的N型晶体管，并且具有第二部分，该第二部分包括具有由 P +源极和漏极区。 绝缘层设置在第一和第二部分之上，在沟道区域上形成薄的绝缘膜。 该方法的步骤包括在绝缘层上施加掩模层，该绝缘层在其中一个部分上具有开口，将第一杂质引入该部分的沟道区域以用于沟道定制目的，在第一绝缘层上沉积第一导电耐火材料 膜，位于该部分的沟道区域上，去除掩模层，将第二杂质引入到另一部分的沟道区域中以用于沟道定制目的，并将第二导电材料沉积在位于 其它部分并与第一导电材料接触。 第一和第二导电材料具有不同的功能。 第一导电材料优选为铂硅化物，而第二导电材料可为铝。