公开(公告)号：US08386864B2

公开(公告)日：2013-02-26

申请号：US13361749

申请日：2012-01-30

Applicant: Prashant Dubey ,  Akhil Garg ,  Sravan Kumar Bhaskarani

Inventor： Prashant Dubey ,  Akhil Garg ,  Sravan Kumar Bhaskarani

IPC: G01R31/28

CPC classification number: G11C29/16 ,  G11C29/1201 ,  G11C29/26 ,  G11C29/32 ,  G11C2029/0401 ,  G11C2029/2602 ,  G11C2029/5602

Abstract: A system and method of sharing testing components for multiple embedded memories and the memory system incorporating the same are disclosed. The memory system includes multiple test controllers, multiple interface devices, a main controller, and a serial interface. The main controller is used for initializing testing of each of the dissimilar memory groups using a serial interface and local test controllers. The memory system results in reduced routing congestion and faster testing of plurality of dissimilar memories. The present disclosure further provides a programmable shared built in self-testing (BIST) architecture utilizing globally asynchronous and locally synchronous (GALS) methodology for testing multiple memories. The built in self-test (BIST) architecture includes a programmable master controller, multiple memory wrappers, and an interface. The interface can be a globally asynchronous and locally synchronous (GALS) interface.

Abstract translation: 公开了一种共享用于多个嵌入式存储器的测试组件的系统和方法以及包含该测试组件的存储器系统。 存储系统包括多个测试控制器，多个接口设备，主控制器和串行接口。 主控制器用于使用串行接口和本地测试控制器初始化每个不同内存组的测试。 存储器系统导致路由拥塞减少和多个不同存储器的更快测试。 本公开还提供了一种利用全局异步和本地同步（GALS）方法来测试多个存储器的可编程共享的内建自测试（BIST）架构。 内置自检（BIST）架构包括可编程主控制器，多个存储器包装器和接口。 该接口可以是全局异步和本地同步（GALS）接口。

公开(公告)号：US08400181B2

公开(公告)日：2013-03-19

申请号：US12769325

申请日：2010-04-28

Applicant: Sravan Kumar Bhaskarani

Inventor： Sravan Kumar Bhaskarani

IPC: G01R31/00

CPC classification number: G01R31/318511

Abstract: A wafer is disclosed that includes a plurality of pipeline interconnected integrated circuit dies that form a plurality of pipelines. A plurality of dies in each pipeline is connected to receive scanned output test data from a neighboring die in a pipeline. A wafer level test access mechanism (TAM) transceiver circuitry, located outside the plurality of pipeline interconnected IC dies, is connected in common to each of the pipelines to provide input test data in a parallel fashion to the plurality of pipelines. The wafer level test access mechanism transceiver circuitry also provides output test results from each of the pipelines for evaluation by a computerized test system. In one embodiment, the wafer level test access mechanism transceiver circuitry is wireless so that it wirelessly receives test data to be passed through the multiple pipelines on a wafer and also includes wireless transmit circuitry to transmit test results from each of the pipelines. When on the wafer, the dies in a pipeline are interconnected with pipeline die test interconnection paths that provide pipeline test information interconnection among the plurality of dies in the pipeline.

Abstract translation: 公开了一种晶片，其包括形成多个管道的多个管道互连集成电路管芯。 每个管道中的多个管芯被连接以在流水线中接收来自相邻管芯的扫描的输出测试数据。 位于多个管道互连IC管芯外部的晶片级测试访问机制（TAM）收发器电路被共同地连接到每个管道，以与多个管道并行地提供输入测试数据。 晶片级测试访问机制收发器电路还提供来自每个管道的输出测试结果，以供计算机化测试系统评估。 在一个实施例中，晶片级测试访问机制收发器电路是无线的，使得其无线地接收要通过晶片上的多个管线的测试数据，并且还包括用于从每个管道传输测试结果的无线传输电路。 当在晶片上时，管道中的模具与管道模具测试互连路径相互连接，其在管道中的多个管芯之间提供管道测试信息互连。

公开(公告)号：US20120198291A1

公开(公告)日：2012-08-02

申请号：US13361749

申请日：2012-01-30

Applicant: Prashant Dubey ,  Akhil Garg ,  Sravan Kumar Bhaskarani

Inventor： Prashant Dubey ,  Akhil Garg ,  Sravan Kumar Bhaskarani

IPC: G11C29/12 ,  G06F11/27

CPC classification number: G11C29/16 ,  G11C29/1201 ,  G11C29/26 ,  G11C29/32 ,  G11C2029/0401 ,  G11C2029/2602 ,  G11C2029/5602

Abstract: A system and method of sharing testing components for multiple embedded memories and the memory system incorporating the same. The memory system includes multiple test controllers, multiple interface devices, a main controller, and a serial interface. The main controller is used for initializing testing of each of the dissimilar memory groups using a serial interface and local test controllers. The memory system results in reduced routing congestion and faster testing of plurality of dissimilar memories. The present disclosure further provides a programmable shared built in self testing (BIST) architecture utilizing globally asynchronous and locally synchronous (GALS) methodology for testing multiple memories. The built in self test (BIST) architecture includes a programmable master controller, multiple memory wrappers, and an interface. The interface can be a globally asynchronous and locally synchronous (GALS) interface.

Abstract translation: 一种共享用于多个嵌入式存储器的测试组件的系统和方法以及包含其的存储器系统。 存储系统包括多个测试控制器，多个接口设备，主控制器和串行接口。 主控制器用于使用串行接口和本地测试控制器初始化每个不同内存组的测试。 存储器系统导致路由拥塞减少和多个不同存储器的更快测试。 本公开还提供了一种使用全局异步和本地同步（GALS）方法来测试多个存储器的可编程共享内建自测试（BIST）架构。 内置自检（BIST）架构包括可编程主控制器，多个存储器包装器和接口。 该接口可以是全局异步和本地同步（GALS）接口。

公开(公告)号：US20110234253A1

公开(公告)日：2011-09-29

申请号：US12769325

申请日：2010-04-28

Applicant: Sravan Kumar Bhaskarani

Inventor： Sravan Kumar Bhaskarani

IPC: G01R31/28

CPC classification number: G01R31/318511

Abstract: A wafer is disclosed that includes a plurality of pipeline interconnected integrated circuit dies that form a plurality of pipelines. A plurality of dies in each pipeline is connected to receive scanned output test data from a neighboring die in a pipeline. A wafer level test access mechanism (TAM) transceiver circuitry, located outside the plurality of pipeline interconnected IC dies, is connected in common to each of the pipelines to provide input test data in a parallel fashion to the plurality of pipelines. The wafer level test access mechanism transceiver circuitry also provides output test results from each of the pipelines for evaluation by a computerized test system. In one embodiment, the wafer level test access mechanism transceiver circuitry is wireless so that it wirelessly receives test data to be passed through the multiple pipelines on a wafer and also includes wireless transmit circuitry to transmit test results from each of the pipelines. When on the wafer, the dies in a pipeline are interconnected with pipeline die test interconnection paths that provide pipeline test information interconnection among the plurality of dies in the pipeline.

Abstract translation: 公开了一种晶片，其包括形成多个管道的多个管道互连集成电路管芯。 每个管道中的多个管芯被连接以在管道中接收来自相邻管芯的扫描的输出测试数据。 位于多个管道互连IC管芯外部的晶片级测试访问机制（TAM）收发器电路被共同地连接到每个管道，以与多个管道并行地提供输入测试数据。 晶片级测试访问机制收发器电路还提供来自每个管道的输出测试结果，以供计算机化测试系统评估。 在一个实施例中，晶片级测试访问机制收发器电路是无线的，使得其无线地接收要通过晶片上的多个管线的测试数据，并且还包括用于从每个管道传输测试结果的无线传输电路。 当在晶片上时，管道中的模具与管道模具测试互连路径相互连接，其在管道中的多个管芯之间提供管道测试信息互连。

公开(公告)号：US08108744B2

公开(公告)日：2012-01-31

申请号：US11891848

申请日：2007-08-13

Applicant: Prashant Dubey ,  Akhil Garg ,  Sravan Kumar Bhaskarani

Inventor： Prashant Dubey ,  Akhil Garg ,  Sravan Kumar Bhaskarani

IPC: G11C29/00 ,  G01R31/28

CPC classification number: G11C29/16 ,  G11C29/1201 ,  G11C29/26 ,  G11C29/32 ,  G11C2029/0401 ,  G11C2029/2602 ,  G11C2029/5602

Abstract: A system and method of sharing testing components for multiple embedded memories and the memory system incorporating the same. The memory system includes multiple test controllers, multiple interface devices, a main controller, and a serial interface. The main controller is used for initializing testing of each of the dissimilar memory groups using a serial interface and local test controllers. The memory system results in reduced routing congestion and faster testing of plurality of dissimilar memories. The present disclosure further provides a programmable shared built in self testing (BIST) architecture utilizing globally asynchronous and locally synchronous (GALS) methodology for testing multiple memories. The built in self test (BIST) architecture includes a programmable master controller, multiple memory wrappers, and an interface. The interface can be a globally asynchronous and locally synchronous (GALS) interface.

Abstract translation: 一种共享用于多个嵌入式存储器的测试组件的系统和方法以及包含其的存储器系统。 存储系统包括多个测试控制器，多个接口设备，主控制器和串行接口。 主控制器用于使用串行接口和本地测试控制器初始化每个不同内存组的测试。 存储器系统导致路由拥塞减少和多个不同存储器的更快测试。 本公开还提供了一种使用全局异步和本地同步（GALS）方法来测试多个存储器的可编程共享内建自测试（BIST）架构。 内置自检（BIST）架构包括可编程主控制器，多个存储器包装器和接口。 该接口可以是全局异步和本地同步（GALS）接口。

公开(公告)号：US20080126892A1

公开(公告)日：2008-05-29

申请号：US11891848

申请日：2007-08-13

Applicant: Prashant Dubey ,  Akhil Garg ,  Sravan Kumar Bhaskarani

Inventor： Prashant Dubey ,  Akhil Garg ,  Sravan Kumar Bhaskarani

IPC: G11C29/00 ,  G01R31/28

CPC classification number: G11C29/16 ,  G11C29/1201 ,  G11C29/26 ,  G11C29/32 ,  G11C2029/0401 ,  G11C2029/2602 ,  G11C2029/5602

Abstract: A system and method of sharing testing components for multiple embedded memories and the memory system incorporating the same. The memory system includes multiple test controllers, multiple interface devices, a main controller, and a serial interface. The main controller is used for initializing testing of each of the dissimilar memory groups using a serial interface and local test controllers. The memory system results in reduced routing congestion and faster testing of plurality of dissimilar memories. The present disclosure further provides a programmable shared built in self testing (BIST) architecture utilizing globally asynchronous and locally synchronous (GALS) methodology for testing multiple memories. The built in self test (BIST) architecture includes a programmable master controller, multiple memory wrappers, and an interface. The interface can be a globally asynchronous and locally synchronous (GALS) interface.

Abstract translation: 一种共享用于多个嵌入式存储器的测试组件的系统和方法以及包含其的存储器系统。 存储系统包括多个测试控制器，多个接口设备，主控制器和串行接口。 主控制器用于使用串行接口和本地测试控制器初始化每个不同内存组的测试。 存储器系统导致路由拥塞减少和多个不同存储器的更快测试。 本公开还提供了一种使用全局异步和本地同步（GALS）方法来测试多个存储器的可编程共享内建自测试（BIST）架构。 内置自检（BIST）架构包括可编程主控制器，多个存储器包装器和接口。 该接口可以是全局异步和本地同步（GALS）接口。