公开(公告)号：US20140070320A1

公开(公告)日：2014-03-13

申请号：US13606768

申请日：2012-09-07

Applicant: Srijit Mukherjee ,  Christopher J. Wiegand ,  Ivler . Weeks ,  Mark Y. Liu ,  Michael L. Hattendorf

Inventor： Srijit Mukherjee ,  Christopher J. Wiegand ,  Ivler . Weeks ,  Mark Y. Liu ,  Michael L. Hattendorf

IPC: H01L27/088 ,  H01L29/66

CPC classification number: H01L21/82385 ,  H01L21/28008 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823821 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/495 ,  H01L29/66477

Abstract: Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.

Abstract translation: 集成电路包括具有选择性凹陷栅电极的MOSFET。 具有具有减小的电容耦合面积到相邻源极和漏极接触金属化的凹陷栅电极的晶体管与具有非凹陷且具有较大z高度的栅电极的晶体管一起提供。 在实施例中，模拟电路采用具有给定z高度的栅电极的晶体管，而逻辑门采用具有较小z高度的凹陷栅电极的晶体管。 在实施例中，基本上平面的栅电极的子集被选择性地回蚀以基于在电路内的给定晶体管的应用来区分栅电极的高度。

公开(公告)号：US20180151423A1

公开(公告)日：2018-05-31

申请号：US15570857

申请日：2015-06-03

Applicant: Christopher J. Jezewski ,  Srijit Mukherjee ,  Daniel B. Bergstrom ,  Tejaswi K. Indukuri ,  Flavio Griggio ,  Ramanan V. Chebiam ,  James S. Clarke

Inventor： Christopher J. Jezewski ,  Srijit Mukherjee ,  Daniel B. Bergstrom ,  Tejaswi K. Indukuri ,  Flavio Griggio ,  Ramanan V. Chebiam ,  James S. Clarke

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76846 ,  H01L21/76843 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53252 ,  H01L23/53266

Abstract: In one embodiment, a conductive connector for a microelectronic component may be formed with a noble metal layer, acting as an adhesion/wetting layer, disposed between a barrier liner and a conductive fill material. In a further embodiment, the conductive connector may have a noble metal conductive fill material disposed directly on the barrier liner. The use of a noble metal as an adhesion/wetting layer or as a conductive fill material may improve gapfill and adhesion, which may result in the conductive connector being substantially free of voids, thereby improving the electrical performance of the conductive connector relative to conductive connectors without a noble metal as the adhesion/wetting layer or the conductive fill material.

公开(公告)号：US08896030B2

公开(公告)日：2014-11-25

申请号：US13606768

申请日：2012-09-07

Applicant: Srijit Mukherjee ,  Christopher J. Wiegand ,  Tyler J. Weeks ,  Mark Y. Liu ,  Michael L. Hattendorf

Inventor： Srijit Mukherjee ,  Christopher J. Wiegand ,  Tyler J. Weeks ,  Mark Y. Liu ,  Michael L. Hattendorf

IPC: H01L27/118 ,  H01L27/088 ,  H01L29/66 ,  H01L27/11

CPC classification number: H01L21/82385 ,  H01L21/28008 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823821 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/495 ,  H01L29/66477

Abstract: Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.

Abstract translation: 集成电路包括具有选择性凹陷栅电极的MOSFET。 具有具有减小的电容耦合面积到相邻源极和漏极接触金属化的凹陷栅电极的晶体管与具有非凹陷且具有较大z高度的栅电极的晶体管一起提供。 在实施例中，模拟电路采用具有给定z高度的栅电极的晶体管，而逻辑门采用具有较小z高度的凹陷栅电极的晶体管。 在实施例中，基本上平面的栅电极的子集被选择性地回蚀以基于在电路内的给定晶体管的应用来区分栅电极的高度。