公开(公告)号：US20190140166A1

公开(公告)日：2019-05-09

申请号：US16097801

申请日：2016-07-01

Applicant: MD Tofizur RAHMAN ,  Christopher J. WIEGAND ,  Brian MAERTZ ,  Daniel G. OUELLETTE ,  Kaan OGUZ ,  Brian S. DOYLE ,  Mark L. DOCZY ,  Daniel B. BERGSTROM ,  Justin S. BROCKMAN ,  Oleg GOLONZKA ,  Tahhir GHANI ,  Intel Corporation

Inventor： MD Tofizur RAHMAN ,  Christopher J. WIEGAND ,  Brian MAERTZ ,  Daniel G. OUELLETTE ,  Kevin P. O'BRIEN ,  Kaan OGUZ ,  Brian S. DOYLE ,  Mark L. DOCZY ,  Daniel B. BERGSTROM ,  Justin S. BROCKMAN ,  Oleg GOLONZKA ,  Tahir GHANI

IPC: H01L43/12 ,  H01L43/10 ,  H01L43/08 ,  H01L43/02 ,  G11C11/16

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: Material layer stack structures to provide a magnetic tunnel junction (MTJ) having improved perpendicular magnetic anisotropy (PMA) characteristics. In an embodiment, a free magnetic layer of the material layer stack is disposed between a tunnel barrier layer and a cap layer of magnesium oxide (Mg). The free magnetic layer includes a Cobalt-Iron-Boron (CoFeB) body substantially comprised of a combination of Cobalt atoms, Iron atoms and Boron atoms. A first Boron mass fraction of the CoFeB body is equal to or more than 25% (e.g., equal to or more than 27%) in a first region which adjoins an interface of the free magnetic layer with the tunnel barrier layer. In another embodiment, the first Boron mass fraction is more than a second Boron mass fraction in a second region of the CoFeB body which adjoins an interface of the free magnetic layer with the cap layer.

公开(公告)号：US20130320453A1

公开(公告)日：2013-12-05

申请号：US13487111

申请日：2012-06-01

Applicant: Abhijit Jayant Pethe ,  Justin S. Sandford ,  Christopher J. Wiegand ,  Robert D. James

Inventor： Abhijit Jayant Pethe ,  Justin S. Sandford ,  Christopher J. Wiegand ,  Robert D. James

IPC: H01L21/336 ,  H01L27/088

CPC classification number: H01L29/66795 ,  H01L29/7854

Abstract: Improving an area scaling on tri-gate transistors is described. An insulating layer is deposited on a fin on a substrate. The insulating layer is recessed to expose the fin. The corner of the fin is rounded off using a noble gas. A gate dielectric layer is deposited on the rounded corner. The radius of curvature of the corner is controllable by adjusting a bias power to the substrate. The radius of curvature of the corner is determined based on the width of the fin to reduce an area scaling of the array.

Abstract translation: 描述了改进三栅极晶体管的面积缩放。 绝缘层沉积在基板上的翅片上。 绝缘层凹入以露出翅片。 翅片的角落使用惰性气体四舍五入。 栅极电介质层沉积在圆角上。 拐角的曲率半径可以通过调节衬底的偏置功率来控制。 基于翅片的宽度来确定拐角的曲率半径以减小阵列的面积缩放。

公开(公告)号：US10804460B2

公开(公告)日：2020-10-13

申请号：US16097801

申请日：2016-07-01

Applicant: MD Tofizur Rahman ,  Christopher J. Wiegand ,  Brian Maertz ,  Daniel G. Ouellette ,  Kaan Oguz ,  Brian S. Doyle ,  Mark L. Doczy ,  Daniel B. Bergstrom ,  Justin S. Brockman ,  Oleg Golonzka ,  Tahir Ghani ,  Intel Corporation

Inventor： MD Tofizur Rahman ,  Christopher J. Wiegand ,  Brian Maertz ,  Daniel G. Ouellette ,  Kevin P. O'Brien ,  Kaan Oguz ,  Brian S. Doyle ,  Mark L. Doczy ,  Daniel B. Bergstrom ,  Justin S. Brockman ,  Oleg Golonzka ,  Tahir Ghani

IPC: H01L29/82 ,  H01L43/12 ,  H01L43/08 ,  H01L43/10 ,  G11C11/16 ,  H01L43/02

Abstract: Material layer stack structures to provide a magnetic tunnel junction (MTJ) having improved perpendicular magnetic anisotropy (PMA) characteristics. In an embodiment, a free magnetic layer of the material layer stack is disposed between a tunnel barrier layer and a cap layer of magnesium oxide (Mg). The free magnetic layer includes a Cobalt-Iron-Boron (CoFeB) body substantially comprised of a combination of Cobalt atoms, Iron atoms and Boron atoms. A first Boron mass fraction of the CoFeB body is equal to or more than 25% (e.g., equal to or more than 27%) in a first region which adjoins an interface of the free magnetic layer with the tunnel barrier layer. In another embodiment, the first Boron mass fraction is more than a second Boron mass fraction in a second region of the CoFeB body which adjoins an interface of the free magnetic layer with the cap layer.

公开(公告)号：US20140070320A1

公开(公告)日：2014-03-13

申请号：US13606768

申请日：2012-09-07

Applicant: Srijit Mukherjee ,  Christopher J. Wiegand ,  Ivler . Weeks ,  Mark Y. Liu ,  Michael L. Hattendorf

Inventor： Srijit Mukherjee ,  Christopher J. Wiegand ,  Ivler . Weeks ,  Mark Y. Liu ,  Michael L. Hattendorf

IPC: H01L27/088 ,  H01L29/66

CPC classification number: H01L21/82385 ,  H01L21/28008 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823821 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/495 ,  H01L29/66477

Abstract: Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.

Abstract translation: 集成电路包括具有选择性凹陷栅电极的MOSFET。 具有具有减小的电容耦合面积到相邻源极和漏极接触金属化的凹陷栅电极的晶体管与具有非凹陷且具有较大z高度的栅电极的晶体管一起提供。 在实施例中，模拟电路采用具有给定z高度的栅电极的晶体管，而逻辑门采用具有较小z高度的凹陷栅电极的晶体管。 在实施例中，基本上平面的栅电极的子集被选择性地回蚀以基于在电路内的给定晶体管的应用来区分栅电极的高度。

公开(公告)号：US08896030B2

公开(公告)日：2014-11-25

申请号：US13606768

申请日：2012-09-07

Applicant: Srijit Mukherjee ,  Christopher J. Wiegand ,  Tyler J. Weeks ,  Mark Y. Liu ,  Michael L. Hattendorf

Inventor： Srijit Mukherjee ,  Christopher J. Wiegand ,  Tyler J. Weeks ,  Mark Y. Liu ,  Michael L. Hattendorf

IPC: H01L27/118 ,  H01L27/088 ,  H01L29/66 ,  H01L27/11

CPC classification number: H01L21/82385 ,  H01L21/28008 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823821 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/495 ,  H01L29/66477

Abstract: Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.

Abstract translation: 集成电路包括具有选择性凹陷栅电极的MOSFET。 具有具有减小的电容耦合面积到相邻源极和漏极接触金属化的凹陷栅电极的晶体管与具有非凹陷且具有较大z高度的栅电极的晶体管一起提供。 在实施例中，模拟电路采用具有给定z高度的栅电极的晶体管，而逻辑门采用具有较小z高度的凹陷栅电极的晶体管。 在实施例中，基本上平面的栅电极的子集被选择性地回蚀以基于在电路内的给定晶体管的应用来区分栅电极的高度。