公开(公告)号：US5968196A

公开(公告)日：1999-10-19

申请号：US63872

申请日：1998-04-21

申请人： Srinivas Ramamurthy ,  Neal Berger ,  James Fahey, Jr. ,  Geoffrey S. Gongwer ,  William J. Saiki ,  Eugene Jinglun Tam

发明人： Srinivas Ramamurthy ,  Neal Berger ,  James Fahey, Jr. ,  Geoffrey S. Gongwer ,  William J. Saiki ,  Eugene Jinglun Tam

IPC分类号： G01R31/28 ,  G01R31/3185

CPC分类号： G01R31/318533 ,  G01R31/318516

摘要： A boundary scan test circuit (JTAG) interface is used to provide data for a set of configuration latches within a Configuration Register. The Configuration Register is included within the JTAG structure as a Test Data Register (TDR). Each configuration bit within the Configuration Register consists of a Configuration Latch, and each configuration latch has an output used as a configuration control signal within an output logic macrocell. The configuration register's input signal is selectably provided from either a set of serially connected configuration bit non-volatile element sense latches or from the JTAG Test Data In (TDI) data pin for reconfiguration, prototyping, and testing.

摘要翻译： 边界扫描测试电路（JTAG）接口用于为配置寄存器内的一组配置锁存器提供数据。 配置寄存器作为测试数据寄存器（TDR）包含在JTAG结​​构内。 配置寄存器中的每个配置位由配置锁存器组成，每个配置锁存器都将输出用作输出逻辑宏单元内的配置控制信号。 配置寄存器的输入信号可从一组串行连接的配置位非易失性元件检测锁存器或JTAG测试数据输入（TDI）数据引脚中进行选择性地提供，用于重新配置，原型设计和测试。

公开(公告)号：US6158034A

公开(公告)日：2000-12-05

申请号：US205651

申请日：1998-12-03

申请人： Srinivas Ramamurthy ,  James Fahey ,  Eugene Jinglun Tam ,  Geoffrey S. Gongwer

发明人： Srinivas Ramamurthy ,  James Fahey ,  Eugene Jinglun Tam ,  Geoffrey S. Gongwer

IPC分类号： G01R31/28 ,  G01R31/3185 ,  G06F11/22

CPC分类号： G01R31/318555

摘要： A JTAG Boundary Scan method by which the on-chip system logic (OCSL) of an integrated circuit is changed by use of a state machine which, among other functions, allows a predefined set of instructions to be loaded into an Instruction Register and then executed. The predefined instructions are designed to follow in sequence after certain other previous instructions. The instructions change the OCSL from one state to another state and allows the state to be changed without the need of a full device reset. Additional instructions within this invention were created to have attendant operating modes for which termination is self timed within the integrated circuit. Additional instructions further control the implementation of instruction execution within the state machine.

摘要翻译： 通过使用状态机来改变集成电路的片上系统逻辑（OCSL）的JTAG边界扫描方法，该状态机除了其他功能之外还允许将预定义的一组指令加载到指令寄存器中然后执行 。 预定义的指令被设计为在某些其它先前的指令之后依次跟随。 指令将OCSL从一个状态更改为另一个状态，并允许更改状态，而无需重置设备。 创建了本发明中的附加说明，以具有在集成电路内终止自适应的伴随操作模式。 附加指令进一步控制状态机内执行指令的执行。

公开(公告)号：US6032279A

公开(公告)日：2000-02-29

申请号：US965919

申请日：1997-11-07

申请人： Srinivas Ramamurthy ,  Jinglun Tam ,  Geoffrey S. Gongwer ,  James Fahey

发明人： Srinivas Ramamurthy ,  Jinglun Tam ,  Geoffrey S. Gongwer ,  James Fahey

IPC分类号： G01R31/28 ,  G01R31/3185

CPC分类号： G01R31/318558

摘要： Boundary Scan integrated circuits are provided with a plurality of new registers between two dedicated pins, Test Data In (TDI) and Test Data Out (TDO) pins. The new registers include an address register and a plurality of test data registers which are addressable by the address register using address-dependent instructions in the instruction register (IR). Instructions for the addressable registers may be steered to the correct register with an ADDLOAD instruction placed in the instruction register followed by an address-dependent instruction. The ADDLOAD instruction makes the address register active between the TDI and TDO pins. Any instruction from a set of address-dependent instructions may be steered to any register handling address-dependent instructions allowing a small number of instructions to be used in a large number of addressable data registers. At the same time non-addressable registers, such as the Boundary Scan register, use address-independent instructions.

摘要翻译： 边界扫描集成电路在两个专用引脚，测试数据输入（TDI）和测试数据输出（TDO）引脚之间提供多个新寄存器。 新的寄存器包括地址寄存器和多个测试数据寄存器，它们可以由地址寄存器使用指令寄存器（IR）中的地址相关指令进行寻址。 可寻址寄存器的指令可以通过放置在指令寄存器中的ADDLOAD指令转向正确的寄存器，后跟地址相关指令。 ADDLOAD指令使地址寄存器在TDI和TDO引脚之间有效。 来自一组地址相关指令的任何指令可被引导到处理地址相关指令的任何寄存器，允许在大量可寻址数据寄存器中使用少量指令。 同时，非寻址寄存器（如边界扫描寄存器）使用地址无关指令。

公开(公告)号：US5848026A

公开(公告)日：1998-12-08

申请号：US986506

申请日：1997-12-08

申请人： Srinivas Ramamurthy ,  Jinglun Eugene Tam ,  Geoffrey S. Gongwer ,  James Fahey, Jr. ,  Neal Berger ,  William Saiki

发明人： Srinivas Ramamurthy ,  Jinglun Eugene Tam ,  Geoffrey S. Gongwer ,  James Fahey, Jr. ,  Neal Berger ,  William Saiki

IPC分类号： G11C16/02 ,  G11C16/10 ,  H04N21/435 ,  H04N21/4405 ,  G11C8/00

CPC分类号： G11C16/10

摘要： Bulk operation logic circuitry for use in carrying out bulk program, erase, verify and margining operations on nonvolatile memory cells of a PLD, FPGA, flash-based microcontroller, EEPROM, flash memory device or other integrated circuit containing such cells includes a flag register for designating one or more selected blocks of cells to which the bulk operation will be limited. The bulk operation circuitry includes a controller, with a state machine and associated control logic, that distributes system clock signals and provides control signals to an instruction register, the flag register, an address register and one or more data registers to control loading of instructions and data into those registers through a serial input. The state machine is responsive to a mode signal for switching it from a normal user state into a bulk operation state. The use of a flag register allows simplification of the instruction set to register load instructions and basic bulk operation instructions (and a flow through operation using a serial output from the registers), while providing a wide variety of possible block selections for the different bulk operations.

摘要翻译： 用于在PLD，FPGA，基于闪存的微控制器，EEPROM，闪速存储器件或包含这种单元的其它集成电路的非易失性存储器单元上执行批量编程，擦除，验证和裕度操作的批量操作逻辑电路包括：标志寄存器 指定将限制批量操作的一个或多个选定的单元块。 大容量操作电路包括具有状态机和相关联的控制逻辑的控制器，其分配系统时钟信号并向控制寄存器，标志寄存器，地址寄存器和一个或多个数据寄存器提供控制信号，以控制指令的加载，以及 通过串行输入将数据写入这些寄存器。 状态机响应于将模式信号从正常用户状态切换到大容量操作状态。 使用标志寄存器可以简化寄存器加载指令和基本批量操作指令（以及使用寄存器的串行输出的操作流程）的指令集，同时为不同的批量操作提供各种可能的块选择 。