公开(公告)号：US5968196A

公开(公告)日：1999-10-19

申请号：US63872

申请日：1998-04-21

申请人： Srinivas Ramamurthy ,  Neal Berger ,  James Fahey, Jr. ,  Geoffrey S. Gongwer ,  William J. Saiki ,  Eugene Jinglun Tam

发明人： Srinivas Ramamurthy ,  Neal Berger ,  James Fahey, Jr. ,  Geoffrey S. Gongwer ,  William J. Saiki ,  Eugene Jinglun Tam

IPC分类号： G01R31/28 ,  G01R31/3185

CPC分类号： G01R31/318533 ,  G01R31/318516

摘要： A boundary scan test circuit (JTAG) interface is used to provide data for a set of configuration latches within a Configuration Register. The Configuration Register is included within the JTAG structure as a Test Data Register (TDR). Each configuration bit within the Configuration Register consists of a Configuration Latch, and each configuration latch has an output used as a configuration control signal within an output logic macrocell. The configuration register's input signal is selectably provided from either a set of serially connected configuration bit non-volatile element sense latches or from the JTAG Test Data In (TDI) data pin for reconfiguration, prototyping, and testing.

摘要翻译： 边界扫描测试电路（JTAG）接口用于为配置寄存器内的一组配置锁存器提供数据。 配置寄存器作为测试数据寄存器（TDR）包含在JTAG结​​构内。 配置寄存器中的每个配置位由配置锁存器组成，每个配置锁存器都将输出用作输出逻辑宏单元内的配置控制信号。 配置寄存器的输入信号可从一组串行连接的配置位非易失性元件检测锁存器或JTAG测试数据输入（TDI）数据引脚中进行选择性地提供，用于重新配置，原型设计和测试。

公开(公告)号：US6158034A

公开(公告)日：2000-12-05

申请号：US205651

申请日：1998-12-03

申请人： Srinivas Ramamurthy ,  James Fahey ,  Eugene Jinglun Tam ,  Geoffrey S. Gongwer

发明人： Srinivas Ramamurthy ,  James Fahey ,  Eugene Jinglun Tam ,  Geoffrey S. Gongwer

IPC分类号： G01R31/28 ,  G01R31/3185 ,  G06F11/22

CPC分类号： G01R31/318555

摘要： A JTAG Boundary Scan method by which the on-chip system logic (OCSL) of an integrated circuit is changed by use of a state machine which, among other functions, allows a predefined set of instructions to be loaded into an Instruction Register and then executed. The predefined instructions are designed to follow in sequence after certain other previous instructions. The instructions change the OCSL from one state to another state and allows the state to be changed without the need of a full device reset. Additional instructions within this invention were created to have attendant operating modes for which termination is self timed within the integrated circuit. Additional instructions further control the implementation of instruction execution within the state machine.

摘要翻译： 通过使用状态机来改变集成电路的片上系统逻辑（OCSL）的JTAG边界扫描方法，该状态机除了其他功能之外还允许将预定义的一组指令加载到指令寄存器中然后执行 。 预定义的指令被设计为在某些其它先前的指令之后依次跟随。 指令将OCSL从一个状态更改为另一个状态，并允许更改状态，而无需重置设备。 创建了本发明中的附加说明，以具有在集成电路内终止自适应的伴随操作模式。 附加指令进一步控制状态机内执行指令的执行。

公开(公告)号：US6032279A

公开(公告)日：2000-02-29

申请号：US965919

申请日：1997-11-07

申请人： Srinivas Ramamurthy ,  Jinglun Tam ,  Geoffrey S. Gongwer ,  James Fahey

发明人： Srinivas Ramamurthy ,  Jinglun Tam ,  Geoffrey S. Gongwer ,  James Fahey

IPC分类号： G01R31/28 ,  G01R31/3185

CPC分类号： G01R31/318558

摘要： Boundary Scan integrated circuits are provided with a plurality of new registers between two dedicated pins, Test Data In (TDI) and Test Data Out (TDO) pins. The new registers include an address register and a plurality of test data registers which are addressable by the address register using address-dependent instructions in the instruction register (IR). Instructions for the addressable registers may be steered to the correct register with an ADDLOAD instruction placed in the instruction register followed by an address-dependent instruction. The ADDLOAD instruction makes the address register active between the TDI and TDO pins. Any instruction from a set of address-dependent instructions may be steered to any register handling address-dependent instructions allowing a small number of instructions to be used in a large number of addressable data registers. At the same time non-addressable registers, such as the Boundary Scan register, use address-independent instructions.

摘要翻译： 边界扫描集成电路在两个专用引脚，测试数据输入（TDI）和测试数据输出（TDO）引脚之间提供多个新寄存器。 新的寄存器包括地址寄存器和多个测试数据寄存器，它们可以由地址寄存器使用指令寄存器（IR）中的地址相关指令进行寻址。 可寻址寄存器的指令可以通过放置在指令寄存器中的ADDLOAD指令转向正确的寄存器，后跟地址相关指令。 ADDLOAD指令使地址寄存器在TDI和TDO引脚之间有效。 来自一组地址相关指令的任何指令可被引导到处理地址相关指令的任何寄存器，允许在大量可寻址数据寄存器中使用少量指令。 同时，非寻址寄存器（如边界扫描寄存器）使用地址无关指令。

公开(公告)号：US5848026A

公开(公告)日：1998-12-08

申请号：US986506

申请日：1997-12-08

申请人： Srinivas Ramamurthy ,  Jinglun Eugene Tam ,  Geoffrey S. Gongwer ,  James Fahey, Jr. ,  Neal Berger ,  William Saiki

发明人： Srinivas Ramamurthy ,  Jinglun Eugene Tam ,  Geoffrey S. Gongwer ,  James Fahey, Jr. ,  Neal Berger ,  William Saiki

IPC分类号： G11C16/02 ,  G11C16/10 ,  H04N21/435 ,  H04N21/4405 ,  G11C8/00

CPC分类号： G11C16/10

摘要： Bulk operation logic circuitry for use in carrying out bulk program, erase, verify and margining operations on nonvolatile memory cells of a PLD, FPGA, flash-based microcontroller, EEPROM, flash memory device or other integrated circuit containing such cells includes a flag register for designating one or more selected blocks of cells to which the bulk operation will be limited. The bulk operation circuitry includes a controller, with a state machine and associated control logic, that distributes system clock signals and provides control signals to an instruction register, the flag register, an address register and one or more data registers to control loading of instructions and data into those registers through a serial input. The state machine is responsive to a mode signal for switching it from a normal user state into a bulk operation state. The use of a flag register allows simplification of the instruction set to register load instructions and basic bulk operation instructions (and a flow through operation using a serial output from the registers), while providing a wide variety of possible block selections for the different bulk operations.

摘要翻译： 用于在PLD，FPGA，基于闪存的微控制器，EEPROM，闪速存储器件或包含这种单元的其它集成电路的非易失性存储器单元上执行批量编程，擦除，验证和裕度操作的批量操作逻辑电路包括：标志寄存器 指定将限制批量操作的一个或多个选定的单元块。 大容量操作电路包括具有状态机和相关联的控制逻辑的控制器，其分配系统时钟信号并向控制寄存器，标志寄存器，地址寄存器和一个或多个数据寄存器提供控制信号，以控制指令的加载，以及 通过串行输入将数据写入这些寄存器。 状态机响应于将模式信号从正常用户状态切换到大容量操作状态。 使用标志寄存器可以简化寄存器加载指令和基本批量操作指令（以及使用寄存器的串行输出的操作流程）的指令集，同时为不同的批量操作提供各种可能的块选择 。

公开(公告)号：US5231312A

公开(公告)日：1993-07-27

申请号：US850285

申请日：1992-03-12

申请人： Geoffrey S. Gongwer ,  Jinglun Tam ,  Keith H. Gudger ,  Joe Yu ,  Steven A. Sharp

发明人： Geoffrey S. Gongwer ,  Jinglun Tam ,  Keith H. Gudger ,  Joe Yu ,  Steven A. Sharp

IPC分类号： H03K19/173

CPC分类号： H03K19/1737

摘要： An integrated circuit package including a plurality of macrocells for connecting a logic circuit of the package to a plurality of external contacts of the package. At least one of the macrocells has an output driver that is enabled or disabled by a control signal for transmitting or preventing transmission of a logic signal to one of the contacts. The control signal is generated by a logic gate that receives and logically combines an individual output enable signal dedicated to that particular macrocell with a selected signal. One signal that may be selected is a regional output enable signal that is supplied to more than one macrocell. Each macrocell also has a feedback multiplexer selecting one signal to be sent to the logic circuit. Choices include a nonstored logic signal, a stored logic signal from a flip-flop register in the macrocell, a signal applied to the external contact associated with that macrocell, and a signal applied to another external contact associated with a different macrocell. A plurality of contacts are connected to feedback multiplexers in two different macrocells, and at least one contact connects in this manner to separate logic regions of the logic circuit. The flip-flop register in the macrocell has a choice of data inputs selected by another multiplexer from among at least one logic signal from the logic circuit and at least one signal applied to an external contact.

摘要翻译： 一种集成电路封装，包括用于将封装的逻辑电路连接到封装的多个外部触点的多个宏单元。 宏单元中的至少一个具有通过控制信号使能或禁用的输出驱动器，用于发送或阻止向一个触点发送逻辑信号。 控制信号由逻辑门产生，该逻辑门接收并逻辑地组合专用于该特定宏小区的单独输出使能信号与所选择的信号。 可以选择的一个信号是被提供给多个宏小区的区域输出使能信号。 每个宏单元还具有选择要发送到逻辑电路的一个信号的反馈多路复用器。 选择包括非存储逻辑信号，来自宏单元中的触发器寄存器的存储逻辑信号，施加到与该宏单元相关联的外部触点的信号，以及施加到与不同宏单元相关联的另一外部触点的信号。 多个触点连接到两个不同宏小区中的反馈多路复用器，并且至少一个触点以这种方式连接到逻辑电路的分离逻辑区。 宏单元中的触发器寄存器具有来自逻辑电路的至少一个逻辑信号和施加到外部触点的至少一个信号的另一多路复用器选择的数据输入的选择。

公开(公告)号：US07245556B1

公开(公告)日：2007-07-17

申请号：US11321217

申请日：2005-12-28

申请人： Yosi Pinto ,  Geoffrey S. Gongwer ,  Oren Honen

发明人： Yosi Pinto ,  Geoffrey S. Gongwer ,  Oren Honen

IPC分类号： G11C8/00

CPC分类号： G11C8/10 ,  G06F12/0246 ,  G06F2212/1036 ,  G06F2212/7211 ,  G11C16/349 ,  G11C16/3495

摘要： A memory system that incorporates methods of amplifying the lifetime of a counter made up of memory elements, such as EEPROM cells, having finite endurance. A relatively small memory made up of a number of individually accessible write segments, where, depending on the embodiment, each write segment is made up of a single memory cell or a small number of cells (e.g., a byte). A count is encoded so that it is distributed across a number of fields, each associated with one of the write segments, such that as the count is incremented only a single field (or, in the single bit embodiments, occasionally more than one field) is changed and that these changes are evenly distributed across the fields. The changed field is then written to the corresponding segment, while the other write segments are unchanged. Consequently, the number of rewrites to a given write segment is decreased, and the lifetime correspondingly increased, by a factor corresponding to the number of write segments used.

摘要翻译： 一种存储系统，其包含放大由具有有限耐久性的诸如EEPROM单元之类的存储元件构成的计数器的寿命的方法。 由多个单独访问的写入段构成的相对小的存储器，其中根据实施例，每个写入段由单个存储器单元或少量单元（例如，一个字节）组成。 计数被编码，使得其分布在多个字段中，每个字段与写入段之一相关联，使得当计数仅增加一个字段（或者在单个实施例中，偶尔地多于一个字段）时， 改变了这些变化是均匀地分布在各个领域。 然后将更改的字段写入相应的段，而其他写段不变。 因此，给定写入段的重写次数减少，并且寿命相应地增加了与所使用的写入段数相对应的因子。

公开(公告)号：US07243275B2

公开(公告)日：2007-07-10

申请号：US11304961

申请日：2005-12-14

申请人： Geoffrey S. Gongwer ,  Daniel C. Guterman ,  Yupin Kawing Fong

发明人： Geoffrey S. Gongwer ,  Daniel C. Guterman ,  Yupin Kawing Fong

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C11/5635 ,  G11C11/5628 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

摘要： A “smart verify” technique, whereby multi-state memories are programmed using a verify-results-based dynamic adjustment of the multi-states verify range for sequential-state-based verify implementations, is presented. This technique can increase multi-state write speed while maintaining reliable operation within sequentially verified, multi-state memory implementations by providing “intelligent” element to minimize the number of sequential verify operations for each program/verify/lockout step of the write sequence. At the beginning of a program/verify cycle sequence only the lowest state or states are checked during the verify phase. As lower states are reached, additional higher states are added to the verify sequence and lower states can be removed.

摘要翻译： 提出了一种“智能验证”技术，其中使用基于验证结果的动态调整多状态验证范围对基于顺序状态的验证实现来编程多状态存储器。 该技术可以通过提供“智能”元件来最小化写入序列的每个程序/验证/锁定步骤的顺序验证操作的数量，从而提高多状态写入速度，同时在顺序验证的多状态存储器实现中保持可靠的操作。 在程序/验证周期序列的开始，在验证阶段只检查最低的状态或状态。 当达到较低的状态时，额外的更高的状态被添加到验证序列中，并且可以去除较低的状态。

公开(公告)号：US07092292B2

公开(公告)日：2006-08-15

申请号：US10976692

申请日：2004-10-28

申请人： Nima Mokhlesi ,  Daniel C. Guterman ,  Geoffrey S. Gongwer

发明人： Nima Mokhlesi ,  Daniel C. Guterman ,  Geoffrey S. Gongwer

IPC分类号： G11C16/04

CPC分类号： G11C11/5642 ,  G11C16/0458 ,  G11C16/26

摘要： The present invention presents methods for reducing the amount of noise inherent in the reading of a non-volatile storage device by applying an episodic agitation (e.g. a time varying voltage) to some terminal(s) of the cell as part of the reading process. Various aspects of the present invention also extend to devices beyond non-volatile memories. According to one aspect of the present invention, in addition to the normal voltage levels applied to the cell as part of the reading process, a time varying voltage is applied to the cell. A set of exemplary embodiments apply a single or multiple set of alternating voltages to one or more terminals of a floating gate memory cell just prior to or during the signal integration time of a read process. In other embodiments, other reproducible external or internal agitations which are repeatable, and whose average effect (from one integration time to the next integration time) remains sufficiently constant so as to have a net noise reduction effect is applicable.

公开(公告)号：US06678192B2

公开(公告)日：2004-01-13

申请号：US10053339

申请日：2001-11-02

申请人： Geoffrey S. Gongwer ,  Shahzad B. Khalid ,  Daniel C. Guterman

发明人： Geoffrey S. Gongwer ,  Shahzad B. Khalid ,  Daniel C. Guterman

IPC分类号： G11C1606

CPC分类号： G11C16/349 ,  G11C11/5621 ,  G11C11/5642 ,  G11C16/28 ,  G11C29/00

摘要： A memory system (e.g., memory card) having error management for stored levels (e.g., reference levels) used in discrimination of logic levels for data storage units providing data storage is disclosed. The stored levels can be stored in predetermined storage units (e.g., writable tracking storage units) in the memory system. The memory system is typically a non-volatile memory product or device that provides binary or multi-state data storage.

摘要翻译： 公开了一种对提供数据存储的数据存储单元的逻辑电平进行辨别的存储电平（例如参考电平）的错误管理的存储器系统（例如，存储卡）。 存储的电平可以存储在存储器系统中的预定存储单元（例如，可写跟踪存储单元）中。 存储器系统通常是提供二进制或多状态数据存储的非易失性存储器产品或设备。

公开(公告)号：US07916552B2

公开(公告)日：2011-03-29

申请号：US12763569

申请日：2010-04-20

申请人： Daniel C. Guterman ,  Stephen J. Gross ,  Shazad Khalid ,  Geoffrey S. Gongwer

发明人： Daniel C. Guterman ,  Stephen J. Gross ,  Shazad Khalid ,  Geoffrey S. Gongwer

IPC分类号： G11C16/04

CPC分类号： G11C16/26 ,  G11C11/5621 ,  G11C16/349

摘要： Tracking cells are used in a memory system to improve the read process. The tracking cells can provide an indication of the quality of the data and can be used as part of a data recovery operation if there is an error. The tracking cells provide a means to adjust the read parameters to optimum levels in order to reflect the current conditions of the memory system. Additionally, some memory systems that use multi-state memory cells will apply rotation data schemes to minimize wear. The rotation scheme can be encoded in the tracking cells based on the states of multiple tracking cells, which is decoded upon reading.

摘要翻译： 在存储器系统中使用跟踪单元来改善读取过程。 跟踪单元可以提供数据质量的指示，如果存在错误，可以将其用作数据恢复操作的一部分。 跟踪单元提供了将读取参数调整到最佳水平以便反映存储器系统的当前状况的手段。 另外，使用多状态存储器单元的一些存储器系统将应用旋转数据方案以最小化磨损。 可以基于多个跟踪单元的状态在跟踪单元中编码旋转方案，该单元在读取时被解码。