Method of etching a layer in a trench and method of fabricating a trench capacitor
    1.
    发明授权
    Method of etching a layer in a trench and method of fabricating a trench capacitor 失效
    在沟槽中蚀刻层的方法和制造沟槽电容器的方法

    公开(公告)号:US06939805B2

    公开(公告)日:2005-09-06

    申请号:US10253196

    申请日:2002-09-24

    摘要: To fabricate a trench capacitor in a substrate, a trench is formed in the substrate. The trench has an upper region and a lower region. In the trench, first of all nanocrystallites and/or a seed layer for nanocrystallites are deposited in the upper region and the lower region. Then, the nanocrystallites and/or the seed layer are removed from the upper region of the trench by means of an etching process. The etching parameters of the etching process are selected in such a way that the seed layer and/or the nanocrystallites which are uncovered in the upper region and the lower region are removed only from the upper region. Consequently, an expensive mask layer can be avoided in the lower region of the trench.

    摘要翻译: 为了在衬底中制造沟槽电容器,在衬底中形成沟槽。 沟槽具有上部区域和下部区域。 在沟槽中,在上部区域和下部区域中首先沉积纳米晶体和/或纳米晶体的晶种层。 然后,通过蚀刻工艺从沟槽的上部区域去除纳米晶体和/或种子层。 选择蚀刻工艺的蚀刻参数,使得在上部区域和下部区域中未被覆盖的种子层和/或纳米晶体仅从上部区域移除。 因此,可以在沟槽的下部区域避免昂贵的掩模层。

    Semiconductor memory cell and method for fabricating the memory cell
    2.
    发明授权
    Semiconductor memory cell and method for fabricating the memory cell 失效
    半导体存储单元及其制造方法

    公开(公告)号:US06828192B2

    公开(公告)日:2004-12-07

    申请号:US10657928

    申请日:2003-09-10

    IPC分类号: H01L218242

    CPC分类号: H01L27/10867 H01L27/10873

    摘要: A trench capacitor is formed in a trench, which is disposed in a substrate. The trench is filled with a conductive trench filling which functions as an inner capacitor electrode. An epitaxial layer is grown on the sidewall of the trench on the substrate. A buried strap is disposed between the conductive trench filling with the second intermediate layer and the epitaxially grown layer. A dopant outdiffusion formed from the buried strap is disposed in the epitaxially grown layer. Through the epitaxially grown layer, the dopant outdiffusion is further removed from a selection transistor disposed beside the trench, as a result of which it is possible to avoid short-channel effects in the selection transistor.

    摘要翻译: 在沟槽中形成沟槽电容器,其设置在基板中。 沟槽填充有用作内部电容器电极的导电沟槽填充物。 在衬底上的沟槽的侧壁上生长外延层。 掩埋带设置在填充有第二中间层的导电沟槽和外延生长层之间。 在外延生长层中设置从掩埋带形成的掺杂剂外扩散。 通过外延生长层,从布置在沟槽旁边的选择晶体管进一步去除掺杂剂扩散,结果可以避免选择晶体管中的短沟道效应。