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公开(公告)号：US07783869B2
公开(公告)日：2010-08-24
申请号：US11641120
申请日：2006-12-19
IPC分类号： G06F9/00
CPC分类号： G06F9/3844 , G06F9/3806
摘要： A data processing apparatus is disclosed that comprises: a processor for processing a stream of decoded instructions; a prefetch unit for fetching instructions within a stream of instructions from a memory prior to sending said stream of instructions to said processor; branch prediction logic operable to predict a behaviour of a branch instruction; a branch target cache for storing predetermined information about branch operations executed by said processor, said predetermined information comprising: identification data for an instruction specifying a branch operation and data relating to whether said branch is taken or not; wherein said data processing apparatus is operable to access said branch target cache and to determine if there is data corresponding to instructions within said stream of instructions stored within said branch target cache and if there is to output said data; said data processing apparatus further comprising: a data store operable to store data indicative of a behaviour of a branch instruction; and said data processing apparatus is operable over a period of time to access predetermined information corresponding to more instructions within said branch target cache than instructions it prefetches from said memory such that said accesses to said branch target cache develop an advance in said instruction stream with respect to accesses to said memory; and said prefetch unit is operable to access said data store and to determine if there is data corresponding to an instruction within said data store that indicates that said instruction specifies a branch operation that will be taken and will cause a change in instruction flow.
摘要翻译： 公开了一种数据处理装置，包括：处理器，用于处理解码指令流; 预取单元，用于在将所述指令流发送到所述处理器之前从存储器中取出指令流内的指令; 分支预测逻辑，用于预测分支指令的行为; 分支目标缓存，用于存储关于由所述处理器执行的分支操作的预定信息，所述预定信息包括：用于指定分支操作的指令的识别数据和与是否采用所述分支有关的数据; 其中所述数据处理装置可操作以访问所述分支目标高速缓存并且确定是否存在与存储在所述分支目标高速缓存内的所述指令流内的指令相对应的数据，以及是否输出所述数据; 所述数据处理装置还包括：数据存储器，用于存储指示分支指令的行为的数据; 并且所述数据处理装置在一段时间内可操作以访问与所述分支目标高速缓存器内的更多指令相对应的预定信息，而不是从其从所述存储器预取的指令，使得对所述分支目标高速缓存的所述访问在所述指令流中相对于 访问所述存储器; 并且所述预取单元可操作以访问所述数据存储并且确定是否存在与所述数据存储器内的指令相对应的数据，其指示所述指令指定将被采用的分支操作，并且将导致指令流程的改变。
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2.发明申请Identification and correction of cyclically recurring errors in one or more branch predictors 有权识别和校正一个或多个分支预测器中的周期性重复错误公开(公告)号：US20090210685A1
公开(公告)日：2009-08-20
申请号：US12071279
申请日：2008-02-19
申请人： Louis-Marie Vincent Mouton , Nicolas Huot , Stephane Eric Sebastien Brochier , Gilles Eric Grandou
发明人： Louis-Marie Vincent Mouton , Nicolas Huot , Stephane Eric Sebastien Brochier , Gilles Eric Grandou
IPC分类号： G06F9/30
CPC分类号： G06F9/3844 , G06F9/3806 , G06F9/3861 , G06F11/0721 , G06F11/0751
摘要： A data processing apparatus 2 is provided with one or more branch predictors 10 for generating branch predictions. A supervising predictor 12 is responsive to at least a stream of branch predictions to identify one or more cyclically recurring errors in the branch predictors and generate corrected behaviours for a prefetch unit 4.
摘要翻译： 数据处理装置2具有用于产生分支预测的一个或多个分支预测器10。 监督预测器12响应于至少一个分支预测流，以识别分支预测器中的一个或多个循环重复的错误，并为预取单元4产生校正的行为。
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公开(公告)号：US20080148028A1
公开(公告)日：2008-06-19
申请号：US11641120
申请日：2006-12-19
IPC分类号： G06F9/38
CPC分类号： G06F9/3844 , G06F9/3806
摘要： A data processing apparatus is disclosed that comprises: a processor for processing a stream of decoded instructions; a prefetch unit for fetching instructions within a stream of instructions from a memory prior to sending said stream of instructions to said processor; branch prediction logic operable to predict a behaviour of a branch instruction; a branch target cache for storing predetermined information about branch operations executed by said processor, said predetermined information comprising: identification data for an instruction specifying a branch operation and data relating to whether said branch is taken or not; wherein said data processing apparatus is operable to access said branch target cache and to determine if there is data corresponding to instructions within said stream of instructions stored within said branch target cache and if there is to output said data; said data processing apparatus further comprising: a data store operable to store data indicative of a behaviour of a branch instruction; and said data processing apparatus is operable over a period of time to access predetermined information corresponding to more instructions within said branch target cache than instructions it prefetches from said memory such that said accesses to said branch target cache develop an advance in said instruction stream with respect to accesses to said memory; and said prefetch unit is operable to access said data store and to determine if there is data corresponding to an instruction within said data store that indicates that said instruction specifies a branch operation that will be taken and will cause a change in instruction flow.
摘要翻译： 公开了一种数据处理装置，包括：处理器，用于处理解码指令流; 预取单元，用于在将所述指令流发送到所述处理器之前从存储器中取出指令流内的指令; 分支预测逻辑，用于预测分支指令的行为; 分支目标缓存，用于存储关于由所述处理器执行的分支操作的预定信息，所述预定信息包括：用于指定分支操作的指令的识别数据和与是否采用所述分支有关的数据; 其中所述数据处理装置可操作以访问所述分支目标高速缓存并且确定是否存在与存储在所述分支目标高速缓存内的所述指令流内的指令相对应的数据，以及是否输出所述数据; 所述数据处理装置还包括：数据存储器，用于存储指示分支指令的行为的数据; 并且所述数据处理装置在一段时间内可操作以访问与所述分支目标高速缓存器内的更多指令相对应的预定信息，而不是从其从所述存储器预取的指令，使得对所述分支目标高速缓存的所述访问在所述指令流中相对于 访问所述存储器; 并且所述预取单元可操作以访问所述数据存储并且确定是否存在与所述数据存储器内的指令相对应的数据，其指示所述指令指定将被采用的分支操作，并且将导致指令流程的改变。
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公开(公告)号：US20080114939A1
公开(公告)日：2008-05-15
申请号：US11599596
申请日：2006-11-15
IPC分类号： G06F12/08
CPC分类号： G06F12/0895 , G06F12/0864 , G06F12/1045 , Y02D10/13
摘要： A data processor operable to process data said data processor comprising: a set associative cache divided into a plurality of cache ways and operable to store data processed by said data processor; a buffer operable to store a table comprising a plurality of mappings of pages of virtual addresses to pages of physical addresses for said data processor; a data store comprising a plurality of data entries each operable to store data for identifying an address of a memory location for each of a plurality of recent cache accesses, each of said plurality of data entries comprising a page index indicating a page in an address space, offset data indicating a location within said page and cache way data identifying a cache way of a cache storage location accessed by said cache access; wherein said data processor is operable in response to a cache access request comprising a virtual address indicating a memory location to access said table and said data store to determine whether said cache access request is to one of said plurality of recently accessed cache storage locations and if so to identify a cache way of said cache storage location from data stored in both said data store and said table.
摘要翻译： 数据处理器，可操作用于处理数据，所述数据处理器包括：分组为多个高速缓存路径并可操作以存储由所述数据处理器处理的数据的集合相关高速缓存; 缓冲器，用于将包括多个虚拟地址页面的表的表存储到所述数据处理器的物理地址页; 数据存储器，其包括多个数据条目，每个数据条目可操作以存储用于识别多个最近高速缓存访问中的每一个的存储器位置的地址的数据，所述多个数据条目中的每一个包括指示地址空间中的页面的页面索引 ，指示所述页面内的位置的偏移数据和标识由所述高速缓存访问访问的高速缓存存储位置的高速缓存方式的高速缓存路数据; 其中所述数据处理器可操作以响应于高速缓存访问请求，所述高速缓存访问请求包括指示访问所述表的存储器位置的虚拟地址和所述数据存储，以确定所述高速缓存访问请求是否是所述多个最近访问的缓存存储位置之一，以及 因此从存储在所述数据存储器和所述表中的数据中识别所述高速缓存存储位置的缓存方式。
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5.发明申请Reusing a buffer memory as a microcache for program instructions of a detected program loop 有权将缓冲存储器重新用作检测到的程序循环的程序指令的微存储器公开(公告)号：US20080172547A1
公开(公告)日：2008-07-17
申请号：US11652148
申请日：2007-01-11
申请人： Frederic Claude Marie Piry , Louis-Marie Vincent Mouton , Stephane Eric Sabastien Brochier , Gilles Eric Grandou
发明人： Frederic Claude Marie Piry , Louis-Marie Vincent Mouton , Stephane Eric Sabastien Brochier , Gilles Eric Grandou
IPC分类号： G06F9/32
CPC分类号： G06F9/381 , G06F9/3814
摘要： A data processing system 2 includes an instruction cache 6 having an associated buffer memory 18, 8. The buffer memory 18, 8 can operate in a buffer mode or in a microcache mode. The buffer memory is switched into the microcache mode upon program loop detection performed by loop detector circuitry 20. When operating in the microcache mode, instruction data is read from the buffer memory 18, 8 without requiring an access to the instruction cache 6.
摘要翻译： 数据处理系统2包括具有相关联的缓冲存储器18,8的指令高速缓存6。 缓冲存储器18,8可以以缓冲模式或微存储模式工作。 在由环路检测器电路20执行的程序循环检测时，缓冲存储器切换到微型缓存模式。 当以微型缓存模式操作时，从缓冲存储器18,8读取指令数据，而不需要访问指令高速缓冲存储器6。
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6.发明授权Reusing a buffer memory as a microcache for program instructions of a detected program loop 有权将缓冲存储器重新用作检测到的程序循环的程序指令的微存储器公开(公告)号：US07571305B2
公开(公告)日：2009-08-04
申请号：US11652148
申请日：2007-01-11
申请人： Fredrick Claude Marie Piry , Louis-Marie Vincent Mouton , Stephane Eric Sabastien Brochier , Gilles Eric Grandou
发明人： Fredrick Claude Marie Piry , Louis-Marie Vincent Mouton , Stephane Eric Sabastien Brochier , Gilles Eric Grandou
IPC分类号： G06F9/40
CPC分类号： G06F9/381 , G06F9/3814
摘要： A data processing system 2 includes an instruction cache 6 having an associated buffer memory 18, 8. The buffer memory 18, 8 can operate in a buffer mode or in a microcache mode. The buffer memory is switched into the microcache mode upon program loop detection performed by loop detector circuitry 20. When operating in the microcache mode, instruction data is read from the buffer memory 18, 8 without requiring an access to the instruction cache 6.
摘要翻译： 数据处理系统2包括具有相关联的缓冲存储器18,8的指令高速缓冲存储器6.缓冲存储器18,8可以以缓存模式或微存储模式操作。 当循环检测器电路20执行程序循环检测时，缓冲存储器被切换到微存储模式。当以微缓存模式操作时，从缓冲存储器18,8读取指令数据，而不需要访问指令高速缓冲存储器6。
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公开(公告)号：US20090235029A1
公开(公告)日：2009-09-17
申请号：US12379615
申请日：2009-02-25
申请人： Louis-Marie Vincent Mouton , Nicolas Jean Phillippe Huot , Gilles Eric Grandou , Stephane Eric Sebastian Brochier
发明人： Louis-Marie Vincent Mouton , Nicolas Jean Phillippe Huot , Gilles Eric Grandou , Stephane Eric Sebastian Brochier
CPC分类号： G06F12/0864
摘要： A data processing apparatus is disclosed that comprises: at least one data processor for processing data; a set associative cache for storing a plurality of values to be processed by said data processor, each value being identified by an address of a memory location within a memory storing said value, said set associative cache being divided into a plurality of cache ways; a data store comprising a plurality of storage locations for storing a plurality of identifiers, each identifier identifying a cache way that a corresponding value from said set associative cache is stored in and each having a valid indicator associated therewith, said plurality of identifiers corresponding to a plurality of values, said plurality of values being values stored in consecutive addresses such that said data store stores identifiers for values stored in a region of said memory; current pointer store for storing a current pointer pointing to a most recently accessed storage location in said data store; offset determining circuitry responsive to a cache access request to determine an offset of an address of said cache access request to an immediately preceding cache access request, said offset determining circuitry being adapted to update said current pointer by said offset amount; and data store lookup circuitry for determining from a size of said data store and said offset if said updated current pointer is pointing to an address within said region and if so said data processor is adapted to identify said cache way from said stored identifier pointed to by said current pointer if it has a valid indicator associated with it.
摘要翻译： 公开了一种数据处理装置，包括：用于处理数据的至少一个数据处理器; 用于存储要由所述数据处理器处理的多个值的集合关联高速缓冲存储器，每个值由存储所述值的存储器内的存储器位置的地址标识，所述集合关联高速缓存被分为多个高速缓存路径; 数据存储器，包括用于存储多个标识符的多个存储位置，每个标识符标识来自所述组相关高速缓存的相应值被存储在每个标识符中，并且每个具有与之相关联的有效指示符的高速缓存方式，所述多个标识符对应于 多个值，所述多个值是存储在连续地址中的值，使得所述数据存储存储存储在所述存储器的区域中的值的标识符; 当前指针存储器，用于存储指向所述数据存储器中最近访问的存储位置的当前指针; 偏移确定电路，响应于高速缓存访问请求，以确定所述高速缓存访问请求的地址偏移到紧接在前的高速缓存访问请求，所述偏移确定电路适于将所述当前指针更新所述偏移量; 以及数据存储查找电路，用于根据所述数据存储器的大小和所述偏移量确定所述更新的当前指针是否指向所述区域内的地址，如果是，则所述数据处理器适于从所述存储的标识符指向的所述标识符 表示当前指针是否具有与之相关联的有效指示符。
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公开(公告)号：US08151055B2
公开(公告)日：2012-04-03
申请号：US12379615
申请日：2009-02-25
申请人： Louis-Marie Vincent Mouton , Nicolas Jean Phillippe Huot , Gilles Eric Grandou , Stephane Eric Sebastian Brochier
发明人： Louis-Marie Vincent Mouton , Nicolas Jean Phillippe Huot , Gilles Eric Grandou , Stephane Eric Sebastian Brochier
IPC分类号： G06F12/00
CPC分类号： G06F12/0864
摘要： A data processing apparatus includes a data processor, and a data store for storing a plurality of identifiers identifying a cache way in which a corresponding value from a set associative cache is stored. The plurality of identifiers corresponding to a plurality of values stored in consecutive addresses such that a data store stores identifiers for values stored in a region of said memory. Included is a current pointer store for pointing to a most recently accessed storage location in said data store and circuitry to determine an offset of an address of said cache access request to an immediately preceding cache access request. Lookup circuitry determines if said pointer is pointing to an address within said region and said data processor identifies said cache way from said stored identifier pointed to by said current pointer if it has a valid indicator associated therewith.
摘要翻译： 数据处理装置包括数据处理器和数据存储器，用于存储识别从存储组合关联高速缓冲存储器的相应值的高速缓存方式的多个标识符。 多个标识符对应于存储在连续地址中的多个值，使得数据存储器存储存储在所述存储器的区域中的值的标识符。 包括用于指向所述数据存储器中最近访问的存储位置的当前指针存储器以及用于确定所述高速缓存访问请求的地址到紧邻的高速缓存访问请求的偏移的电路。 查找电路确定所述指针是否指向所述区域内的地址，并且如果所述指针具有与其相关联的有效指示符，则所述数据处理器从所述当前指针指向的所存储的标识符中识别所述高速缓存方式。
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9.发明授权Identifying a cache way of a cache access request using information from the microtag and from the micro TLB 有权使用来自微标签和微型TLB的信息来识别缓存访问请求的缓存方式公开(公告)号：US07596663B2
公开(公告)日：2009-09-29
申请号：US11599596
申请日：2006-11-15
IPC分类号： G06F12/00
CPC分类号： G06F12/0895 , G06F12/0864 , G06F12/1045 , Y02D10/13
摘要： A data processor operable to process data said data processor comprising: a set associative cache divided into a plurality of cache ways and operable to store data processed by said data processor; a buffer operable to store a table comprising a plurality of mappings of pages of virtual addresses to pages of physical addresses for said data processor; a data store comprising a plurality of data entries each operable to store data for identifying an address of a memory location for each of a plurality of recent cache accesses, each of said plurality of data entries comprising a page index indicating a page in an address space, offset data indicating a location within said page and cache way data identifying a cache way of a cache storage location accessed by said cache access; wherein said data processor is operable in response to a cache access request comprising a virtual address indicating a memory location to access said table and said data store to determine whether said cache access request is to one of said plurality of recently accessed cache storage locations and if so to identify a cache way of said cache storage location from data stored in both said data store and said table.
摘要翻译： 数据处理器，可操作用于处理数据，所述数据处理器包括：分组为多个高速缓存路径并可操作以存储由所述数据处理器处理的数据的集合相关高速缓存; 缓冲器，用于将包括多个虚拟地址页面的表的表存储到所述数据处理器的物理地址页; 数据存储器，其包括多个数据条目，每个数据条目可操作以存储用于识别多个最近高速缓存访问中的每一个的存储器位置的地址的数据，所述多个数据条目中的每一个包括指示地址空间中的页面的页面索引 ，指示所述页面内的位置的偏移数据和标识由所述高速缓存访问访问的高速缓存存储位置的高速缓存方式的高速缓存路数据; 其中所述数据处理器可操作以响应于高速缓存访问请求，所述高速缓存访问请求包括指示访问所述表的存储器位置的虚拟地址和所述数据存储，以确定所述高速缓存访问请求是否是所述多个最近访问的缓存存储位置之一，以及 因此从存储在所述数据存储器和所述表中的数据中识别所述高速缓存存储位置的缓存方式。
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10.发明授权Apparatus and method for handling access operations issued to local cache structures within a data processing apparatus 有权用于处理发送到数据处理装置内的本地高速缓存结构的访问操作的装置和方法公开(公告)号：US08706965B2
公开(公告)日：2014-04-22
申请号：US13067491
申请日：2011-06-03
IPC分类号： G06F12/00
CPC分类号： G06F12/0842 , G06F9/52 , G06F12/0808 , G06F12/0831 , G06F12/0837 , G06F12/1027
摘要： An apparatus and method are provided for handling access operations issued to local cache structures within a data processing apparatus. The data processing apparatus comprises a plurality of processing units each having a local cache structure associated therewith. Shared access coordination circuitry is also provided for coordinating the handling of shared access operations issued to any of the local cache structures. For a shared access operation, the access control circuitry associated with the local cache structure to which that shared access operation is issued will perform a local access operation to that local cache structure, and in addition will issue a shared access signal to the shared access coordination circuitry. For a local access operation, the access control circuitry would normally perform a local access operation on the associated local cache structure, and not notify the shared access coordination circuitry. However, if an access operation extension value is set, then the access control circuitry treats such a local access operation as a shared access operation. Such an approach ensures correction operation even after an operating system and/or an application program are migrated from one processing unit to another.
摘要翻译： 提供了一种用于处理发送到数据处理设备内的本地高速缓存结构的接入操作的装置和方法。 数据处理装置包括多个处理单元，每个处理单元具有与其相关联的本地缓存结构。 还提供了共享访问协调电路，用于协调对任何本地高速缓存结构发布的共享访问操作的处理。 对于共享访问操作，与发布该共享访问操作的本地高速缓存结构相关联的访问控制电路将执行对该本地高速缓存结构的本地访问操作，并且另外将向共享访问协调发出共享访问信号 电路。 对于本地访问操作，访问控制电路通常将在相关联的本地高速缓存结构上执行本地访问操作，并且不通知共享访问协调电路。 然而，如果设置了访问操作扩展值，则访问控制电路将这样的本地访问操作视为共享访问操作。 即使在操作系统和/或应用程序从一个处理单元迁移到另一个处理单元之后，这种方法也确保校正操作。
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