公开(公告)号：US06552567B1

公开(公告)日：2003-04-22

申请号：US09964664

申请日：2001-09-28

申请人： Brian Boles ,  Richard Fischer ,  Sumit Mitra ,  Rodney Drake ,  Stephen A. Bowling ,  Bryan Kris ,  Steven Marsh ,  Hassan Harb

发明人： Brian Boles ,  Richard Fischer ,  Sumit Mitra ,  Rodney Drake ,  Stephen A. Bowling ,  Bryan Kris ,  Steven Marsh ,  Hassan Harb

IPC分类号： H03K190175

CPC分类号： G06F15/76

摘要： The present invention relates generally to functional pathway configurations at the interfaces between integrated circuits (ICs) and the circuit assemblies with which the ICs communicate. More particularly, the present invention relates generally to the functional pathway configuration at the interface between one or more semiconductor integrated circuit dice, including an IC package and the circuitry of a system wherein the integrated circuit dice is a digital signal controller. Even more particularly, the present invention relates to a 18, 28, 40, 44, 64 or 80 pin functional pathway configuration for the interface between the digital signal controller and the system in which it is embedded.

摘要翻译： 本发明一般涉及集成电路（IC）与IC连接的电路组件之间的接口上的功能通路配置。 更具体地说，本发明一般涉及包括IC封装的一个或多个半导体集成电路管芯与系统的电路之间的界面处的功能通路配置，其中集成电路管芯是数字信号控制器。 更具体地，本发明涉及用于数字信号控制器和嵌入其中的系统之间的接口的18,28,40,44,64或80引脚功能通路配置。

公开(公告)号：US06975679B2

公开(公告)日：2005-12-13

申请号：US09870454

申请日：2001-06-01

申请人： Stephen A. Bowling

发明人： Stephen A. Bowling

IPC分类号： G06F1/025 ,  H02P27/08 ,  H03K7/08

CPC分类号： G06F1/025 ,  H02P27/08 ,  H03K7/08

摘要： Configuration bits are provided that configure PWM outputs of a processor incorporating a PWM module. The configuration bits cause the PWM module to put the PWM outputs into tri-state, active high or active low modes when the PWM module is inactive or when individual PWM outputs are not enabled. The configuration bits are stored in non-volatile memory and perform the configuration after power-up of the processor and after a reset when the PWM module is generally in an inactive state.

摘要翻译： 提供了配置位，其配置包含PWM模块的处理器的PWM输出。 配置位会使PWM模块将PWM输出置为三态，高电平有效或低电平有效模式，当PWM模块无效或单个PWM输出未使能时。 配置位存储在非易失性存储器中，并在处理器上电后并且在PWM模块通常处于非活动状态时复位后执行配置。

公开(公告)号：US06937084B2

公开(公告)日：2005-08-30

申请号：US09870626

申请日：2001-06-01

申请人： Stephen A. Bowling

发明人： Stephen A. Bowling

IPC分类号： H02M1/00 ,  H02M1/38 ,  H03K5/151 ,  H03K7/08 ,  H03K17/296

CPC分类号： H02M1/38 ,  H03K5/1515 ,  H03K7/08

摘要： A processor that has pulse width modulation generation circuitry that provides an improved ability to deal with the less than perfect switching characteristics of external switching devices that are connected to PWM hardware included in a processor. Complementary PWM output signals have dual deadtime delay in which the delay between the inactivation of the first signal and the activation of the second signal may be different than the delay between the inactivation of the second signal and the activation of the first signal. This provides an improved capability to deal with non-symmetric switching characteristics of the external switching devices, and the circuitry to which they are connected. The dual deadtime pulse width modulation generator for a processor includes deadtime generation circuitry operable to generate a first pulse width modulated signal and a second pulse width modulated signal complementary to the first pulse width modulated signal, wherein there is a first delay between inactivation of the first pulse width modulated signal and activation of the second pulse width modulated signal, a second delay between inactivation of the second pulse width modulated signal and activation of the first pulse width modulated signal, and the first and second delays are not equal. The first delay and the second delay may be independently settable.

摘要翻译： 具有脉冲宽度调制生成电路的处理器，其提供了处理连接到处理器中包括的PWM硬件的外部开关器件的不太完美的开关特性的改进能力。 互补PWM输出信号具有双死区时间延迟，其中第一信号的失活和第二信号的激活之间的延迟可能不同于第二信号的失活和第一信号的激活之间的延迟。 这提供了处理外部开关器件及其连接的电路的非对称开关特性的改进的能力。 用于处理器的双死区时间脉宽调制发生器包括死区产生电路，其可操作以产生与第一脉宽调制信号互补的第一脉宽调制信号和第二脉宽调制信号，其中在第一 脉冲宽度调制信号和第二脉冲宽度调制信号的激活，第二脉冲宽度调制信号的失活和第一脉冲宽度调制信号的激活之间的第二延迟以及第一和第二延迟不相等。 第一延迟和第二延迟可以是独立可设定的。

公开(公告)号：US06552625B2

公开(公告)日：2003-04-22

申请号：US09870650

申请日：2001-06-01

申请人： Stephen A. Bowling

发明人： Stephen A. Bowling

IPC分类号： H03K0708

CPC分类号： H02P27/08 ,  G05B2219/34217

摘要： A processor that has pulse width modulation generation circuitry that provides an improved capability to deal with fault conditions, and particularly with multiple concurrent fault conditions, occurring in external circuitry and devices that are connected to PWM hardware included in a processor. A pulse width modulation generator for a processor includes fault priority circuitry having a plurality of fault inputs operable to receive fault input signals and a fault output operable to output a fault output signal, the fault priority circuitry operable to receive fault input signals on a plurality of fault inputs concurrently, and output a fault output signal corresponding to a fault input having a highest priority among the fault inputs that are receiving fault input signals, and pulse width modulation circuitry having at least one pulse width modulation output operable to output at least one pulse width modulated signal and a fault input operable to receive the fault output signal from the fault priority circuitry, the pulse width modulation circuitry operable to drive the pulse width modulation output to a defined state associated with the selected fault input.