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公开(公告)号：US06961715B1
公开(公告)日：2005-11-01
申请号：US09652895
申请日：2000-08-31
CPC分类号： G06T1/60
摘要： A data processing device uses a portion of a random access memory as an input buffer for holding a portion of a stream of data which is being processed by a processing unit within the processing device. Various break-point source tasks 801a–n determine discontinuities in the portion of data stored in the input buffer and a sorted list of the addresses of the discontinuities is maintained in breakpoint queue 800. Since the buffer is managed in a FIFO manner, a single breakpoint register 810 is sufficient to monitor addresses as they are provided by an address register 820 for accessing the random access memory. When a breakpoint is detected, the breakpoint queue and the breakpoint register is updated by an update task 802.
摘要翻译： 数据处理装置使用随机存取存储器的一部分作为输入缓冲器，用于保持由处理装置内的处理单元处理的数据流的一部分。 各种断点源任务801a-n确定存储在输入缓冲器中的数据部分中的不连续性，并且在断点队列800中保持不连续性地址的排序列表。 由于以FIFO方式管理缓冲器，所以单个断点寄存器810足以监视地址寄存器820提供的用于访问随机存取存储器的地址。 当检测到断点时，更新任务802更新断点队列和断点寄存器。
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公开(公告)号：US06272615B1
公开(公告)日：2001-08-07
申请号：US08851573
申请日：1997-05-02
IPC分类号： G06F1200
CPC分类号： G06F9/355 , G06F9/3004 , G06F9/30061 , G06F9/30167 , G06F9/322 , G06F9/325 , G06F9/345 , G06F9/35 , G06F9/383
摘要： A data processing device is provided with an indexed-immediate addressing mode for processing streams of data. An instruction register 900 receives an instruction for execution. Decoding circuitry 913 selects a register specified by a field in an instruction to provide an index value. An immediate field from the instruction is combined with the index value by multiplexor 910 to form an address which can be used to access a data value or to form a target address for a branch instruction. Mux control 915 parses the immediate value to determine how to combine the immediate value and the index value.
摘要翻译： 数据处理设备具有用于处理数据流的索引立即寻址模式。 指令寄存器900接收执行指令。 解码电路913选择由指令中的字段指定的寄存器以提供索引值。 来自指令的立即字段与索引值通过多路复用器910组合以形成可用于访问数据值或形成分支指令的目标地址的地址。 Mux控制915解析立即值，以确定如何组合立即值和索引值。
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公开(公告)号：US5835793A
公开(公告)日：1998-11-10
申请号：US851168
申请日：1997-05-02
CPC分类号： G06F9/30018 , G06F12/04
摘要： A data processing device uses a portion of a random access memory as an input buffer 114 for holding a portion of a stream of data which is being processed by a processing unit within the processing device. A Get Bit-Field instruction is provided which directs the processing unit to extract selected bit fields from the data stream stored in the input buffer. A register R6 holds a bit address which points to the end of a selected bit field, while a register R0 holds the width of the selected bit field. An address register is connected to a register R6 in a manner that allows data words to be accessed in input buffer 114 using only a word portion of the bit address. A funnel shifter 203 is disposed to extract the selected bit field from concatenated data words in response to a bit address portion of the bit address in register R6.
摘要翻译： 数据处理装置使用随机存取存储器的一部分作为输入缓冲器114，用于保持由处理装置内的处理单元处理的数据流的一部分。 提供获取位字段指令，其指示处理单元从存储在输入缓冲器中的数据流中提取所选位字段。 寄存器R6保持指向所选位字段结束的位地址，而寄存器R0保持所选位字段的宽度。 地址寄存器以只允许位地址的字部分在输入缓冲器114中访问数据字的方式连接到寄存器R6。 漏斗移位器203设置成响应于寄存器R6中的位地址的位地址部分从连接的数据字中提取所选择的位域。
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公开(公告)号：US20080222370A1
公开(公告)日：2008-09-11
申请号：US12045267
申请日：2008-03-10
申请人： Fitzgerald J Archibald , Stephen Hsiao-Yi Li , Michael O. Polley , Mohamed F. Mansour , Ramesh Naidu G
发明人： Fitzgerald J Archibald , Stephen Hsiao-Yi Li , Michael O. Polley , Mohamed F. Mansour , Ramesh Naidu G
IPC分类号： G06F12/00
CPC分类号： G06F9/30018
摘要： A method and apparatus of managing data stream, the method comprising archiving received data in a circular buffer; utilizing a breakpoint in realizing the archived received data continuity, wherein the breakpoint is set to the last data portion of the archived received data; when the archiving of the received data approaches the end of the circular buffer, stitching the last portion of the archived received data to the start of the circular buffer; and setting the breakpoint to the updated last data portion of the archived data.
摘要翻译： 一种管理数据流的方法和装置，所述方法包括将接收的数据归档在循环缓冲器中; 利用断点实现存档的接收数据连续性，其中断点被设置为归档接收数据的最后数据部分; 当接收到的数据的归档接近循环缓冲器的末尾时，将存档的接收数据的最后部分拼接到循环缓冲器的开头; 并将断点设置为归档数据的更新的最后数据部分。
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公开(公告)号：US5860060A
公开(公告)日：1999-01-12
申请号：US850404
申请日：1997-05-02
CPC分类号： H04B14/04 , G11B20/00992 , G11B20/18 , H04S1/007
摘要： A data processing device uses a portion of random access memory 121 as an output buffer 124 for holding a portion of a stream of PCM data which is to be output to a digital to analog converter 530. D/A 530 forms a left analog channel and a right analog channel for speaker subsystems 814 and 815. The PCM data stream is stored in the output buffer so that PCM data samples which pertain to the left channel are stored at even address and PCM data samples which pertain to the right channel are stored at odd address. Control circuitry 145 monitors direct memory access (DMA) transfers which transfer PCM data samples to PCM serializer 142. By comparing the address of each DMA transfer to a left/right channel signal from the D/A, the control circuitry can verify that channel synchronization is correct. If a synchronization error is detected, an channel synchronization error correction procedure is invoked.
摘要翻译： 数据处理装置使用随机存取存储器121的一部分作为输出缓冲器124，用于保持要输出到数模转换器530的PCM数据流的一部分.D / A 530形成左模拟通道， 用于扬声器子系统814和815的右模拟通道。PCM数据流存储在输出缓冲器中，使得与左声道相关的PCM数据采样被存储在偶数地址处，并且将与右声道相关的PCM数据样本存储在 奇地址。 控制电路145监视将PCM数据样本传送到PCM串行化器142的直接存储器访问（DMA）传送。通过将每个DMA传输的地址与来自D / A的左/右声道信号进行比较，控制电路可以验证信道同步 是正确的。 如果检测到同步错误，则调用信道同步纠错过程。
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公开(公告)号：US06230278B1
公开(公告)日：2001-05-08
申请号：US08850872
申请日：1997-05-02
申请人： Stephen (Hsiao Yi) Li , Jonathan Rowlands , Fuk Ho Pius Ng , Maria B. H. Gill , Frank L. Laczko, Sr. , Dong-Seok Youm , David (Shiu) W. Kam
发明人： Stephen (Hsiao Yi) Li , Jonathan Rowlands , Fuk Ho Pius Ng , Maria B. H. Gill , Frank L. Laczko, Sr. , Dong-Seok Youm , David (Shiu) W. Kam
IPC分类号： G06F128
CPC分类号： G06F9/3879 , G06F1/3203 , G06F1/3287 , G06F9/30018 , G06F9/30145 , G06F9/30167 , G06F9/355 , G06F9/3877 , Y02D10/171
摘要： A data processing device is provided which has multiprocessors that can be configured on a cycle by cycle basis as loosely coupled or tightly coupled. Bit-stream Processing Unit (BPU) 110 executes instructions from ROM 112 and accesses data from RAM 111. Similarly, Arithmetic Unit (AU) 120 executes instructions from ROM 122 and accesses data from RAM 121. Both processor operate in parallel and exchange data by accessing RAM 121. AU 120 can receive an instruction directive from BPU 110 directing it to perform a selected sequence of instructions in a loosely coupled manner. AU 120 can also receive an instruction directive from BPU 110 directing that a portion of AU 120 operationally replace a portion of BPU 110 for the duration of one instruction which allows data to be passed directly between the processors in a tightly coupled manner.
摘要翻译： 提供了一种数据处理装置，其具有可以以逐周期为基础配置为松散耦合或紧密耦合的多处理器。 位流处理单元（BPU）110执行来自ROM 112的指令并从RAM 111访问数据。类似地，算术单元（AU）120执行来自ROM 122的指令并从RAM 121访问数据。两个处理器并行操作并且通过 访问RAM 121.AU 120可以从BPU 110接收指令，指示它以松散耦合的方式执行选定的指令序列。 AU 120还可以接收来自BPU 110的指令，指示AU 120的一部分在一个指令的持续时间内可操作地替换BPU 110的一部分，这允许以紧密耦合的方式直接在处理器之间传递数据。
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7.发明授权Method and apparatus for downmixing decoded data streams in the frequency domain prior to conversion to the time domain 失效在将转换成时域之前的频域中的解码数据流进行降混的方法和装置
公开(公告)号：US5946352A
公开(公告)日：1999-08-31
申请号：US851575
申请日：1997-05-02
申请人： Jonathan Rowlands , Stephen (Hsiao Yi) Li , Frank L. Laczko, Sr. , Maria B.H. Gill , David (Shiu W.) Kam , Dong-Seok Youm
发明人： Jonathan Rowlands , Stephen (Hsiao Yi) Li , Frank L. Laczko, Sr. , Maria B.H. Gill , David (Shiu W.) Kam , Dong-Seok Youm
CPC分类号： G10L19/008
摘要： A data processing device is programmed to decode and transform a stream of data representing a plurality of subband encoded channels of audio data into one or more channels of PCM encoded data for reproduction by a speaker subsystem. An improved method for decoding and transforming utilizes downmix matrices (1021 and 1022) to form downmixed frequency domain channels in buffers (1031-1034). Only two long DCT transform operations (1041 and 1042) and two short DCT transform operations (1043 and 1044) are needed to transform the downmixed frequency domain channels into a left PCM output (1071) and a right PCM output (1072).
摘要翻译： 数据处理装置被编程为将表示多个子带编码的音频数据的信道的数据流解码和变换成PCM编码数据的一个或多个通道，以便由扬声器子系统再现。 一种用于解码和变换的改进方法利用下混合矩阵（1021和1022）在缓冲器（1031-1034）中形成下混频道信道。 需要两个长的DCT变换操作（1041和1042）和两个短的DCT变换操作（1043和1044）来将下混合的频域通道变换成左PCM输出（1071）和右PCM输出（1072）。
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8.发明授权Method and apparatus for providing fast interrupt response using a ghost instruction 失效使用鬼指令提供快速中断响应的方法和装置
公开(公告)号：US5931934A
公开(公告)日：1999-08-03
申请号：US850431
申请日：1997-05-02
CPC分类号： G06F9/4812
摘要： A data processing device 100 uses a portion of a random access memory 111 as an input buffer for holding a portion of a stream of data which is received by an input interface 130. Likewise, a portion of a memory 121 is used as an output buffer for holding a portion of processed data which is output by an output interface 140. A processing unit 110 within the processing device manages the flow of input and output data. The input interface asserts an I/O request 860 when it receives a data word, and the output interface asserts an I/O request 870 when it needs a data word. In response to an I/O request, fast interrupt circuitry inserts a ghost instruction which is formed by doppelganger circuitry into an instruction sequence which is being accessed from a ROM 112. The ghost instruction performs the requested data transfer.
摘要翻译： 数据处理装置100使用随机存取存储器111的一部分作为输入缓冲器，用于保存由输入接口130接收的数据流的一部分。同样地，存储器121的一部分被用作输出缓冲器 用于保持由输出接口140输出的处理数据的一部分。处理设备内的处理单元110管理输入和输出数据的流程。 当接收到数据字时，输入接口置位I / O请求860，当输出接口需要数据字时，输出接口置位I / O请求870。 响应于I / O请求，快速中断电路将由doppelganger电路形成的重影指令插入到从ROM 112进行访问的指令序列中。幻影指令执行所请求的数据传送。
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公开(公告)号：US06985783B2
公开(公告)日：2006-01-10
申请号：US09827644
申请日：2001-04-06
CPC分类号： G06F9/355 , G06F9/3004 , G06F9/30061 , G06F9/30167 , G06F9/322 , G06F9/325 , G06F9/345 , G06F9/35 , G06F9/383
摘要： A data processing device is provided with an indexed-immediate addressing mode for processing streams of data. An instruction register 900 receives an instruction for execution. Decoding circuitry 913 selects a register specified by a field in an instruction to provide an index value. An immediate field from the instruction is combined with the index value by multiplexor 910 to form an address which can be used to access a data value or to form a target address for a branch instruction. Mux control 915 parses the immediate value to determine how to combine the immediate value and the index value.
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10.发明授权Fine-grained synchronization of a decompressed audio stream by skipping or repeating a variable number of samples from a frame 失效通过从帧中跳过或重复可变数量的样本，解压缩音频流的细粒度同步公开(公告)号：US06310652B1
公开(公告)日：2001-10-30
申请号：US08851574
申请日：1997-05-02
IPC分类号： H04J306
CPC分类号： G10L21/04
摘要： A data processing device uses a portion of a random access memory as an output buffer for holding a frame of PCM sample data which is being output after being processed by a processing unit within the processing device. Fine grained synchronization between a reference clock and a stream of PCM data frames is provided by transferring only a portion of selected frame of PCM sample data PCM(n+1), in response to a time difference 971. A breakpoint address is determined to delineate the portion of the selected frame that is to be transferred. A sorted list of the addresses of the discontinuities is maintained in breakpoint queue. Since the buffer is managed in a FIFO manner, a single breakpoint register is sufficient to monitor addresses as they are provided by an address register for accessing the random access memory. When a breakpoint is detected, the breakpoint queue and the breakpoint register is updated by an update task 802.
摘要翻译： 数据处理装置使用随机存取存储器的一部分作为输出缓冲器，用于保持由处理装置内的处理单元处理之后输出的PCM采样数据的帧。 响应于时间差971，通过仅传送PCM采样数据PCM（n + 1）的所选帧的一部分来提供参考时钟和PCM数据帧流之间的细粒度同步。断点地址被确定为描绘 要传输的所选帧的部分。 在断点队列中维护不连续地址的排序列表。 由于以FIFO方式管理缓冲器，所以单个断点寄存器足以监视地址寄存器提供的访问随机存取存储器的地址。 当检测到断点时，更新任务802更新断点队列和断点寄存器。
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