公开(公告)号：US20070115606A1

公开(公告)日：2007-05-24

申请号：US11164377

申请日：2005-11-21

Applicant: Kenneth DeVries ,  Nancy Greco ,  Joan Preston ,  Stephen Runyon

Inventor： Kenneth DeVries ,  Nancy Greco ,  Joan Preston ,  Stephen Runyon

IPC: H05F3/02 ,  H05F3/00 ,  H01H47/00

CPC classification number: H01L23/5226 ,  H01L21/743 ,  H01L23/5286 ,  H01L23/585 ,  H01L23/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods and structures and methods of designing structures for charge dissipation in an integrated circuit on an SOI substrate. A first structure includes a charge dissipation ring around a periphery of the integrated circuit chip and one or more charge dissipation pedestals physically and electrically connected to the charge dissipation pedestals. The silicon layer and bulk silicon layer of the SOI substrate are connected by the guard ring and the charge dissipation pedestals. The ground distribution grid of the integrated circuit chip is connected to an uppermost wire segment of one or more charge dissipation pedestals. A second structure, replaces the charge dissipation guard ring with additional charge dissipation pedestal elements.

Abstract translation: 在SOI衬底上集成电路中设计电荷耗散结构的方法和结构及方法。 第一结构包括围绕集成电路芯片的周边的电荷耗散环以及物理和电连接到电荷消耗基座的一个或多个电荷消耗基座。 SOI衬底的硅层和体硅层通过保护环和电荷消耗基座连接。 集成电路芯片的地面配电网连接到一个或多个电荷消耗基座的最上面的线段。 第二种结构，用额外的电荷消耗基座元件代替电荷消除保护环。

公开(公告)号：US20070106968A1

公开(公告)日：2007-05-10

申请号：US11164044

申请日：2005-11-08

Applicant: James Culp ,  Lars Liebmann ,  Rajeev Malik ,  K. Paul Muller ,  Shreesh Narasimha ,  Stephen Runyon ,  Patrick Williams

Inventor： James Culp ,  Lars Liebmann ,  Rajeev Malik ,  K. Paul Muller ,  Shreesh Narasimha ,  Stephen Runyon ,  Patrick Williams

IPC: G06F17/50

CPC classification number: G06F17/5068

Abstract: An iterative timing analysis is analytically performed before a chip is fabricated, based on a methodology using optical proximity correction techniques for shortening the gate lengths and adjusting metal line widths and proximity distances of critical time sensitive devices. The additional mask is used as a selective trim to form shortened gate lengths or wider metal lines for the selected, predetermined transistors, affecting the threshold voltages and the RC time constants of the selected devices. Marker shapes identify a predetermined subgroup of circuitry that constitutes the devices in the critical timing path. The analysis methodology is repeated as often as needed to improve the timing of the circuit with shortened designed gate lengths and modified RC timing constants until manufacturing limits are reached. A mask is made for the selected critical devices using OPC techniques.

Abstract translation: 基于使用光学邻近校正技术的方法，在制造芯片之前分析地执行迭代时序分析，以缩短栅极长度并调整关键时间敏感器件的金属线宽度和接近距离。 附加掩模用作选择性修整以形成用于所选择的预定晶体管的缩短的栅极长度或更宽的金属线，影响所选器件的阈值电压和RC时间常数。 标记形状识别构成关键定时路径中的装置的电路的预定子组。 根据需要经常重复分析方法，以在缩短设计的栅极长度和修改的RC定时常数的情况下改善电路的时序，直到达到制造限值。 使用OPC技术为所选的关键设备制作掩码。

公开(公告)号：US20070042579A1

公开(公告)日：2007-02-22

申请号：US11207074

申请日：2005-08-18

Applicant: Stephen Runyon ,  Scott Stiffler

Inventor： Stephen Runyon ,  Scott Stiffler

IPC: H01L21/265

CPC classification number: H01L29/7833 ,  H01L21/26513 ,  H01L21/823807 ,  H01L29/6659 ,  H01L29/7843

Abstract: A system and method for ensuring the migratability of circuits into future technologies while minimizing fabrication costs and maintaining or improving power efficiency are provided. A mask layer is introduced to portions of the integrated circuit prior to a stress inducing layer being applied to the integrated circuit. In an exemplary embodiment of the present invention, a tensile or compressive film is applied to the devices on the integrated circuit chip but is removed from those devices whose operation is to be modified. Thereafter, a tensile or compressive strain layer is applied to the devices whose film was removed. An additional mask layer may then be used to effect a halo or well implant to relax the strain on the devices not being protected by the mask layer. In this way, the current of the non-protected devices is reduced back to its original target design point.

Abstract translation: 提供了一种确保电路迁移到未来技术中同时最小化制造成本并维持或提高功率效率的系统和方法。 在将应力感应层施加到集成电路之前，将掩模层引入到集成电路的部分。 在本发明的示例性实施例中，拉伸或压缩薄膜被施加到集成电路芯片上的器件上，但是从要进行修改的器件移除。 此后，将拉伸或压缩应变层施加到其膜去除的装置上。 然后可以使用另外的掩模层来实现光晕或井注入，以松弛未被掩模层保护的器件上的应变。 以这种方式，无保护设备的电流减少到原来的目标设计点。

公开(公告)号：US20060085768A1

公开(公告)日：2006-04-20

申请号：US10711959

申请日：2004-10-15

Applicant: Fook-Luen Heng ,  Jason Hibbeler ,  Kevin McCullen ,  Rani Narayan ,  Stephen Runyon ,  Robert Walker

Inventor： Fook-Luen Heng ,  Jason Hibbeler ,  Kevin McCullen ,  Rani Narayan ,  Stephen Runyon ,  Robert Walker

IPC: G06F17/50

CPC classification number: G06F17/5068

Abstract: Methods, systems and program products are disclosed for selectively scaling an integrated circuit (IC) design: by layer, by unit, or by ground rule, or a combination of these. The selective scaling technique can be applied in a feedback loop with the manufacturing system with process and yield feedback, during the life of a design, to increase yield in early processes in such a way that hierarchy is preserved. The invention removes the need to involve designers in improving yield where new technologies such as maskless fabrication are implemented.

Abstract translation: 公开了用于选择性地缩放集成电路（IC）设计的方法，系统和程序产品：按层，单元或基本规则，或这些的组合。 在设计寿命期间，选择性缩放技术可以应用于具有过程和产量反馈的制造系统的反馈回路中，以便以保持层次结构的方式增加早期过程中的产量。 本发明消除了在实现诸如无掩模制造之类的新技术的情况下使设计人员改进产量的需要。

公开(公告)号：US20070234260A1

公开(公告)日：2007-10-04

申请号：US11278162

申请日：2006-03-31

Applicant: Christopher Gonzalez ,  Michael Gray ,  Matthew Guzowski ,  Jason Hibbeler ,  Stephen Runyon ,  Xiaoyun Wu

Inventor： Christopher Gonzalez ,  Michael Gray ,  Matthew Guzowski ,  Jason Hibbeler ,  Stephen Runyon ,  Xiaoyun Wu

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F2217/08

Abstract: A method of modifying a VLSI layout for performance optimization includes defining a revised set of ground rules for a plurality of original device shapes to be modified and flattening the plurality of original device shapes to a prime cell. A layout optimization operation is performed on the flattened device shapes, based on the revised set of ground rules, so as to create a plurality of revised device shapes. An overlay cell is then created from a difference between the revised device shapes and the original device shapes.

Abstract translation: 修改用于性能优化的VLSI布局的方法包括为要修改的多个原始设备形状定义修改的基本规则集，并将多个原始设备形状平坦化为初级单元。 基于经修改的基础规则集，对平坦化的设备形状执行布局优化操作，以便创建多个修改的设备形状。 然后从修改的设备形状和原始设备形状之间的差异创建覆盖单元。