公开(公告)号：US20070161290A1

公开(公告)日：2007-07-12

申请号：US11306668

申请日：2006-01-06

Applicant: John Fitzsimmons ,  William Cote ,  Nancy Greco ,  Thomas Ivers ,  Steven Moskowitz

Inventor： John Fitzsimmons ,  William Cote ,  Nancy Greco ,  Thomas Ivers ,  Steven Moskowitz

IPC: H01R13/648

CPC classification number: H01L21/76826 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76825 ,  Y10T29/49117 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: Methods for forming conductor contacts provide for etching through a capping layer located upon a conductor contact region within a substrate. A first pair of methods provide for etching through at least a lower thickness of the capping layer with other than a reactive ion etch to provide an exposed conductor contact region. A partially overlapping second pair of methods provides for converting at least an upper thickness of the capping layer to a converted material layer that is removed incident to providing an exposed conductor contact region. As adjunct to any of the methods, a liner layer is formed and located upon the exposed conductor contact region in absence of an undesirable reactive environment.

Abstract translation: 用于形成导体触点的方法提供了通过位于衬底内的导体接触区域上的覆盖层的蚀刻。 第一对方法提供用除了反应离子蚀刻之外的至少较薄厚度的覆盖层的蚀刻以提供暴露的导体接触区域。 部分重叠的第二对方法提供了将覆盖层的至少上部厚度转换成被去除的转换材料层，以提供暴露的导体接触区域。 作为任何方法的辅助，在没有不期望的反应性环境的情况下，形成衬里层并且位于暴露的导体接触区域上。

公开(公告)号：US20050242442A1

公开(公告)日：2005-11-03

申请号：US10835953

申请日：2004-04-30

Applicant: Nancy Greco ,  Stephen Greco ,  Erik Hedberg

Inventor： Nancy Greco ,  Stephen Greco ,  Erik Hedberg

IPC: H01L21/44 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76895 ,  H01L24/05 ,  H01L2224/05624 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/01029 ,  H01L2924/00

Abstract: Custom connections between pairs of copper wires in a last damascene wiring level are effected by creating openings in an overlying insulating layer which span a distance between portions of the two wires, then filling the openings with aluminum. The openings can be created (or completed) by a second, maskless UV laser exposure of positive photoresist which is used for patterning the insulating layer. If an opening is not created, an aluminum connecting shape overlying the insulating layer will not effect a connection between the two wires. Similar results can be achieved by laser exposure of a resist used to pattern the aluminum layer, thereby causing breaks in connecting shape when it is desired not to have a connection.

Abstract translation: 在最后一个镶嵌布线层次中的铜线对之间的定制连接是通过在覆盖的绝缘层中形成开口，跨越两条线的部分之间的距离，然后用铝填充开口。 可以通过用于图案化绝缘层的正性光致抗蚀剂的第二次无掩模UV激光曝光来创建（或完成）开口。 如果不产生开口，则覆盖绝缘层的铝连接形状将不会影响两条电线之间的连接。 通过用于图案化铝层的抗蚀剂的激光曝光可以实现类似的结果，从而当期望不连接时会导致连接形状的断裂。

公开(公告)号：US20050037568A1

公开(公告)日：2005-02-17

申请号：US10658036

申请日：2003-09-09

Applicant: Nancy Greco ,  David Harame ,  Gary Hueckel ,  Joseph Kocis ,  Dominique Ngoc ,  Kenneth Stein

Inventor： Nancy Greco ,  David Harame ,  Gary Hueckel ,  Joseph Kocis ,  Dominique Ngoc ,  Kenneth Stein

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522 ,  H01L21/8242

CPC classification number: H01L23/5223 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interconnection wiring system incorporating two levels of interconnection wiring separated by a first dielectric, a capacitor formed by a second dielectric, a bottom electrode of the lower interconnection wiring or a via and a top electrode of the upper interconnection wiring or a separate metal layer. The invention overcomes the problem of leakage current and of substrate stray capacitance by positioning the capacitor between two levels of interconnection wiring.

Abstract translation: 一种互连布线系统，包括由第一介质隔离的两层互连布线，由第二介质形成的电容器，下互连布线的底电极或通孔，以及上互连布线的顶电极或单独的金属层。 本发明通过将电容器放置在两层互连布线之间来克服漏电流和衬底杂散电容的问题。

公开(公告)号：US20070261969A1

公开(公告)日：2007-11-15

申请号：US11382802

申请日：2006-05-11

Applicant: Nancy Greco ,  Kimberly Hooper ,  Kevin Petrarca

Inventor： Nancy Greco ,  Kimberly Hooper ,  Kevin Petrarca

IPC: C23F13/00

CPC classification number: C23F13/04 ,  H01L21/02063 ,  H01L21/67057

Abstract: A method and apparatus for cleaning a wafer with a metal exposed through an insulator, through the use of a wet cleaning tank in concert with a feedback system on the potential difference between two leads of the wet cleaning tank. The cleaning tank has a bath in which the wafer and the two leads are immersed. The potential difference between the two leads is regulated when the feedback system detects a change in the potential across the two leads.

Abstract translation: 一种通过使用湿式清洗槽与反馈系统一起使用通过绝缘子暴露的金属来清洁晶片的方法和装置，该方法和装置关于湿式清洗槽的两根引线之间的电位差。 清洗槽具有浸没晶片和两根引线的槽。 当反馈系统检测到两个引线上的电位变化时，两个引线之间的电位差被调节。

公开(公告)号：US20090228312A1

公开(公告)日：2009-09-10

申请号：US12042553

申请日：2008-03-05

Applicant: John P. Cazares ,  Nancy Greco ,  Charles B. Grizzaffi ,  Sanjay Gupta ,  Aditi Jaggi ,  Victor P. Lesmana ,  Jana Palmer ,  Arvin T. Poole ,  Bharat P. Shah

Inventor： John P. Cazares ,  Nancy Greco ,  Charles B. Grizzaffi ,  Sanjay Gupta ,  Aditi Jaggi ,  Victor P. Lesmana ,  Jana Palmer ,  Arvin T. Poole ,  Bharat P. Shah

IPC: G06Q10/00

CPC classification number: G06Q10/109 ,  G06Q10/06 ,  G06Q10/063116 ,  G06Q10/101

Abstract: A method for the creation of timesheets, workload management and analysis includes: receiving a set of individual activity entries in the form of task assignments and workload claim codes into a resource and activity planning tool; exporting individual activity entries from the set of individual activity entries to one or more individual user files; populating one or more individual user calendars with entries from the one or more corresponding individual user files; converting the one or more calendar entries into data format files; generating timesheet and workload data from the data format files; uploading the timesheet and workload data into a workload and data warehouse; and providing the timesheet and workload data for analysis.

Abstract translation: 创建时间表，工作负载管理和分析的方法包括：以任务分配和工作负载索赔代码的形式将一组单独的活动条目接收到资源和活动计划工具中; 将各个活动条目的个别活动条目导出到一个或多个单独的用户文件; 用一个或多个相应的单个用户文件的条目填充一个或多个单独的用户日历; 将一个或多个日历条目转换成数据格式文件; 从数据格式文件生成时间表和工作负载数据; 将时间表和工作负载数据上传到工作负载和数据仓库中; 并提供时间表和工作负载数据进行分析。

公开(公告)号：US06335151B1

公开(公告)日：2002-01-01

申请号：US09335609

申请日：1999-06-18

Applicant: Christopher P. Ausschnitt ,  Nancy Greco ,  Ernest N. Levine

Inventor： Christopher P. Ausschnitt ,  Nancy Greco ,  Ernest N. Levine

IPC: G03F900

CPC classification number: G02B26/0833 ,  G02B3/0012 ,  G03F1/50

Abstract: A lithographic process for creation and replication of well-controlled surfaces of arbitrary profiles on a sub-micron scale. The surfaces are defined by a mathematical function using a binary mask, consisting partly or wholly of subresolution features, and a photoresist film of pre-specified absorption and thickness. The process comprises the steps of (a) creating a mask, (b) imaging the mask pattern on an absorbing photoresist film to a predetermined thickness, and (c) transferring the three dimensional surface to a substrate.

Abstract translation: 用于在亚微米尺度上创建和复制任意轮廓的良好控制表面的光刻工艺。 表面由使用二进制掩模的数学函数定义，二进制掩模部分或全部由亚分辨特征组成，以及具有预定吸收和厚度的光致抗蚀剂膜。 该方法包括以下步骤：（a）制备掩模，（b）将吸收光致抗蚀剂膜上的掩模图案成像到预定厚度，和（c）将三维表面转印到基底上。

公开(公告)号：US5846884A

公开(公告)日：1998-12-08

申请号：US879727

申请日：1997-06-20

Applicant: Munir D. Naeem ,  Stuart M. Burns ,  Nancy Greco ,  Steve Greco ,  Virinder Grewal ,  Ernest Levine ,  Masaki Narita ,  Bruno Spuler

Inventor： Munir D. Naeem ,  Stuart M. Burns ,  Nancy Greco ,  Steve Greco ,  Virinder Grewal ,  Ernest Levine ,  Masaki Narita ,  Bruno Spuler

IPC: C23F4/00 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/00

CPC classification number: H01L21/32136

Abstract: A method in a plasma processing chamber for etching through a selected portion of a layer stack. The layer stack comprises a metallization layer, a first barrier layer disposed adjacent to the metallization layer, and a photoresist layer disposed above the metallization layer. The method includes etching at least partially through the first barrier layer using a high sputter component etch. The method further includes etching at least partially through the metallization layer using a low sputter component etch. The low sputter component etch has a sputter component lower than a sputter component of the high sputter component etch.

Abstract translation: 一种等离子体处理室中用于蚀刻通过层堆叠的选定部分的方法。 层叠包括金属化层，邻近金属化层设置的第一阻挡层和设置在金属化层上方的光致抗蚀剂层。 该方法包括使用高溅射元件蚀刻至少部分地蚀刻第一阻挡层。 该方法还包括使用低溅射元件蚀刻至少部分地蚀刻金属化层。 低溅射元件蚀刻具有低于高溅射元件蚀刻的溅射元件的溅射元件。

公开(公告)号：US20070115606A1

公开(公告)日：2007-05-24

申请号：US11164377

申请日：2005-11-21

Applicant: Kenneth DeVries ,  Nancy Greco ,  Joan Preston ,  Stephen Runyon

Inventor： Kenneth DeVries ,  Nancy Greco ,  Joan Preston ,  Stephen Runyon

IPC: H05F3/02 ,  H05F3/00 ,  H01H47/00

CPC classification number: H01L23/5226 ,  H01L21/743 ,  H01L23/5286 ,  H01L23/585 ,  H01L23/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods and structures and methods of designing structures for charge dissipation in an integrated circuit on an SOI substrate. A first structure includes a charge dissipation ring around a periphery of the integrated circuit chip and one or more charge dissipation pedestals physically and electrically connected to the charge dissipation pedestals. The silicon layer and bulk silicon layer of the SOI substrate are connected by the guard ring and the charge dissipation pedestals. The ground distribution grid of the integrated circuit chip is connected to an uppermost wire segment of one or more charge dissipation pedestals. A second structure, replaces the charge dissipation guard ring with additional charge dissipation pedestal elements.

Abstract translation: 在SOI衬底上集成电路中设计电荷耗散结构的方法和结构及方法。 第一结构包括围绕集成电路芯片的周边的电荷耗散环以及物理和电连接到电荷消耗基座的一个或多个电荷消耗基座。 SOI衬底的硅层和体硅层通过保护环和电荷消耗基座连接。 集成电路芯片的地面配电网连接到一个或多个电荷消耗基座的最上面的线段。 第二种结构，用额外的电荷消耗基座元件代替电荷消除保护环。