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14 条记录 (耗时 0.03 秒)

    OPC TRIMMING FOR PERFORMANCE
    1.
    发明申请
    OPC TRIMMING FOR PERFORMANCE 失效

    公开(公告)号：US20070106968A1

    公开(公告)日：2007-05-10

    申请号：US11164044

    申请日：2005-11-08

    申请人： James Culp ,  Lars Liebmann ,  Rajeev Malik ,  K. Paul Muller ,  Shreesh Narasimha ,  Stephen Runyon ,  Patrick Williams

    发明人： James Culp ,  Lars Liebmann ,  Rajeev Malik ,  K. Paul Muller ,  Shreesh Narasimha ,  Stephen Runyon ,  Patrick Williams

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068

    摘要： An iterative timing analysis is analytically performed before a chip is fabricated, based on a methodology using optical proximity correction techniques for shortening the gate lengths and adjusting metal line widths and proximity distances of critical time sensitive devices. The additional mask is used as a selective trim to form shortened gate lengths or wider metal lines for the selected, predetermined transistors, affecting the threshold voltages and the RC time constants of the selected devices. Marker shapes identify a predetermined subgroup of circuitry that constitutes the devices in the critical timing path. The analysis methodology is repeated as often as needed to improve the timing of the circuit with shortened designed gate lengths and modified RC timing constants until manufacturing limits are reached. A mask is made for the selected critical devices using OPC techniques.

    摘要翻译： 基于使用光学邻近校正技术的方法，在制造芯片之前分析地执行迭代时序分析，以缩短栅极长度并调整关键时间敏感器件的金属线宽度和接近距离。 附加掩模用作选择性修整以形成用于所选择的预定晶体管的缩短的栅极长度或更宽的金属线，影响所选器件的阈值电压和RC时间常数。 标记形状识别构成关键定时路径中的装置的电路的预定子组。 根据需要经常重复分析方法，以在缩短设计的栅极长度和修改的RC定时常数的情况下改善电路的时序，直到达到制造限值。 使用OPC技术为所选的关键设备制作掩码。

    Multilayer OPC for Design Aware Manufacturing
    2.
    发明申请
    Multilayer OPC for Design Aware Manufacturing 失效
    用于设计感知制造的多层OPC

    公开(公告)号：US20070220476A1

    公开(公告)日：2007-09-20

    申请号：US11306750

    申请日：2006-01-10

    申请人： Maharaj Mukherjee ,  James Culp ,  Lars Liebmann ,  Scott Mansfield

    发明人： Maharaj Mukherjee ,  James Culp ,  Lars Liebmann ,  Scott Mansfield

    IPC分类号： G06F17/50

    CPC分类号： G03F1/36

    摘要： A method is provided for designing a mask layout for an integrated circuit that ensures proper functional interaction among circuit features by including functional inter-layer and intra-layer constraints on the wafer. The functional constraints used according to the present invention are applied among the simulated wafer images to ensure proper functional interaction, while relaxing or eliminating the EPE constraints on the location of the wafer images.

    摘要翻译： 提供了一种用于设计用于集成电路的掩模布局的方法，其通过在晶片上包括功能层间和层内约束来确保电路特征之间的适当的功能交互。 根据本发明使用的功能约束应用于模拟晶片图像中，以确保正确的功能交互，同时放松或消除对晶片图像的位置的EPE约束。

    Double Exposure Double Resist Layer Process For Forming Gate Patterns
    3.
    发明申请
    Double Exposure Double Resist Layer Process For Forming Gate Patterns 失效
    双重曝光双抗蚀层工艺形成栅格图案

    公开(公告)号：US20070212863A1

    公开(公告)日：2007-09-13

    申请号：US11308106

    申请日：2006-03-07

    申请人： Timothy Brunner ,  James Culp ,  Lars Liebmann

    发明人： Timothy Brunner ,  James Culp ,  Lars Liebmann

    IPC分类号： H01L21/467

    CPC分类号： H01L21/76895 ,  H01L21/0274 ,  H01L21/28035 ,  H01L21/28123

    摘要： A method of forming a planar CMOS transistor divides the step of forming the gate layer into a first step of patterning a resist layer with a first portion of the gate layer pattern and then etching the polysilicon with the pattern of the gates. A second step patterns a second resist layer with the image of the gate pads and local interconnect and then etching the polysilicon with the pattern of the gate pads and local interconnect, thereby reducing the number of diffraction and other cross-talk from different exposed areas.

    摘要翻译： 形成平面CMOS晶体管的方法将形成栅极层的步骤分成用栅极层图案的第一部分图案化抗蚀剂层，然后用栅极图案蚀刻多晶硅的第一步骤。 第二步利用栅极焊盘和局部互连的图像来形成第二抗蚀剂层，然后用栅极焊盘和局部互连的图案蚀刻多晶硅，从而减少来自不同曝光区域的衍射数量和其它串扰。

    DESIGN VERIFICATION
    7.
    发明申请
    DESIGN VERIFICATION 失效
    设计验证

    公开(公告)号：US20060270268A1

    公开(公告)日：2006-11-30

    申请号：US10908786

    申请日：2005-05-26

    申请人： James Bruce ,  James Culp ,  John Nickel ,  Jacek Smolinski

    发明人： James Bruce ,  James Culp ,  John Nickel ,  Jacek Smolinski

    IPC分类号： H01R4/24

    CPC分类号： G06F17/5081

    摘要： A design verification method, including (a) providing in a design a design electrically conducting line and a design contact region being in direct physical contact with the design electrically conducting line; (b) modeling a simulated electrically conducting line of the design electrically conducting line; (c) simulating a possible contact region of the design contact region, wherein the design contact region and the possible contact region are not identical; and (d) determining that the design electrically conducting line and the design contact region are potentially defective if an interfacing surface area of the simulated electrically conducting line and the possible contact region is less than a pre-specified value.

    摘要翻译： 一种设计验证方法，包括（a）在设计中提供与设计导电线直接物理接触的设计导电线和设计接触区; （b）对设计导电线的模拟导电线进行建模; （c）模拟设计接触区域的可能的接触区域，其中设计接触区域和可能的接触区域不相同; 以及（d）如果所述模拟导电线路和所述可能接触区域的接口表面积小于预定值，则确定所述设计导电线路和所述设计接触区域具有潜在的缺陷。

    Mask inspection process accounting for mask writer proximity correction
    8.
    发明申请
    Mask inspection process accounting for mask writer proximity correction 失效
    掩模检查过程负责掩模写入器邻近校正

    公开(公告)号：US20050117795A1

    公开(公告)日：2005-06-02

    申请号：US10725854

    申请日：2003-12-02

    申请人： Karen Badger ,  James Culp ,  Azalia Krasnoperova

    发明人： Karen Badger ,  James Culp ,  Azalia Krasnoperova

    IPC分类号： G03F7/20 ,  G06F17/50 ,  G06K9/00

    CPC分类号： G03F7/70441

    摘要： A mask inspection method and system. Provided is a mask fabrication database describing geometrical shapes S to be printed as part of a mask pattern on a reticle to fabricate a mask through use of a mask fabrication tooling. The shapes S appear on the mask as shapes S′ upon being printed. At least one of the shapes S′ may be geometrically distorted relative to a corresponding at least one of the shapes S due to a lack of precision in the mask fabrication tooling. Also provided is a mask inspection database to be used for inspecting the mask after the mask has been fabricated by the mask fabrication tooling. The mask inspection database describes shapes S″ approximating the shapes S′. A geometric distortion between the shapes S′ and S″ is less than a corresponding geometric distortion between the shapes S′ and S.

    摘要翻译： 面罩检查方法和系统。 提供了一种掩模制造数据库，其描述要在掩模版上作为掩模图案的一部分打印的几何形状S，以通过使用掩模制造工具来制造掩模。 形状S在印刷时作为形状S'出现在掩模上。 由于在掩模制造工具中缺乏精度，至少一种形状S'可能相对于形状S中的相应的至少一个形状几何失真。 还提供了掩模检查数据库，用于在通过掩模制造工具制造掩模之后检查掩模。 掩模检查数据库描述形状S'近似形状S'。 形状S'和S“之间的几何变形小于形状S'和S之间的对应的几何变形。