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    Memory interface to bridge memory buses
    2.
    发明授权
    Memory interface to bridge memory buses 有权
    内存接口桥接内存总线

    公开(公告)号：US07558124B2

    公开(公告)日：2009-07-07

    申请号：US11277650

    申请日：2006-03-28

    申请人： Larry Wu ,  Gang Shan ,  Stephen Tai ,  Howard Yang ,  Zhen-Dong Guo

    发明人： Larry Wu ,  Gang Shan ,  Stephen Tai ,  Howard Yang ,  Zhen-Dong Guo

    IPC分类号： G11C7/10

    CPC分类号： G11C5/066 ,  G11C5/04 ,  H05K1/181

    摘要： A memory interface to bridge a parallel memory bus and a serial memory bus. A printed circuit board includes at least one memory interface buffer chip to connect a memory controller of core logic and an advanced memory buffer (AMB). The memory controller has a memory interface for a parallel memory bus.

    摘要翻译： 用于桥接并行存储器总线和串行存储器总线的存储器接口。 印刷电路板包括至少一个用于连接核心逻辑的存储器控​​制器和高级存储器缓冲器（AMB）的存储器接口缓冲器芯片。 存储器控制器具有用于并行存储器总线的存储器接口。

    CMOS integrated super-heterodyne television receiver with multiple signal paths
    3.
    发明申请
    CMOS integrated super-heterodyne television receiver with multiple signal paths 有权
    具有多个信号路径的CMOS集成超外差电视接收机

    公开(公告)号：US20080012986A1

    公开(公告)日：2008-01-17

    申请号：US11338872

    申请日：2006-01-24

    申请人： Stephen Tai

    发明人： Stephen Tai

    IPC分类号： H04N3/27 ,  H03J5/00 ,  H04B1/18

    CPC分类号： H03F3/72 ,  H03F3/189

    摘要： Integrated super-heterodyne television receivers with multiple signal paths implemented using CMOS technology. An integrated circuit, includes: a plurality of CMOS (Complementary Metal-Oxide Semiconductor) low noise amplifiers; an adjustable frequency source; and one or more down-conversion mixers coupled with the adjustable frequency source and the plurality of CMOS low noise amplifiers to form a plurality of super-heterodyne receiving paths between an input to the plurality of CMOS low noise amplifiers and an output from one or more down-conversion mixers; where the integrated circuit is implemented on a single chip of semiconductive substrate.

    摘要翻译： 具有使用CMOS技术实现的多个信号路径的集成超外差电视接收机。 一种集成电路，包括：多个CMOS（互补金属氧化物半导体）低噪声放大器; 可调频源; 以及与可调频率源和多个CMOS低噪声放大器耦合的一个或多个下变频混频器，以在多个CMOS低噪声放大器的输入和来自一个或多个CMOS低噪声放大器的输出之间形成多个超外差接收路径 下转换混频器; 其中集成电路在单芯片半导体衬底上实现。

    On-Chip Supply Regulators
    4.
    发明申请
    On-Chip Supply Regulators 有权
    片上电源调节器

    公开(公告)号：US20070285122A1

    公开(公告)日：2007-12-13

    申请号：US11423869

    申请日：2006-06-13

    申请人： Xiaomin Si ,  Howard Yang ,  Stephen Tai

    发明人： Xiaomin Si ,  Howard Yang ,  Stephen Tai

    IPC分类号： H03K19/173 ,  G06F7/38

    CPC分类号： G06F1/26

    摘要： Integrated circuit chips with on-chip supply regulators with programmability and initialization. In one embodiment, an integrated circuit, includes: an initialization circuit to assert an initialization signal during powering up of the integrated circuit; a control circuit coupled to the initialization circuit; and a power supply regulator coupled to the control circuit, the power supply regulator to provide a first voltage to the control circuit when the initialization signal is asserted, the power supply regulator to provide a second voltage to the control circuit according to a control signal from the control circuit when the initialization signal is not asserted. In one embodiment, the integrated circuit includes a digital television demodulator.

    摘要翻译： 具有片上电源调节器的集成电路芯片，具有可编程性和初始化功能。 在一个实施例中，集成电路包括：初始化电路，用于在集成电路加电期间断言初始化信号; 耦合到所述初始化电路的控制电路; 以及耦合到所述控制电路的电源调节器，所述电源调节器在所述初始化信号被断言时向所述控制电路提供第一电压，所述电源调节器根据来自所述控制信号的控制信号向所述控制电路提供第二电压 当初始化信号未被置位时，控制电路。 在一个实施例中，集成电路包括数字电视解调器。

    MEMORY INTERFACE TO BRIDGE MEMORY BUSES
    5.
    发明申请
    MEMORY INTERFACE TO BRIDGE MEMORY BUSES 有权
    内存接口到桥接记忆总线

    公开(公告)号：US20070121389A1

    公开(公告)日：2007-05-31

    申请号：US11277650

    申请日：2006-03-28

    申请人： Larry Wu ,  Howard Yang ,  Zhen-Dong Guo ,  Gang Shan ,  Stephen Tai

    发明人： Larry Wu ,  Howard Yang ,  Zhen-Dong Guo ,  Gang Shan ,  Stephen Tai

    IPC分类号： G11C7/10 ,  G06F12/00

    CPC分类号： G11C5/066 ,  G11C5/04 ,  H05K1/181

    摘要： A memory interface to bridge a parallel memory bus and a serial memory bus. One embodiment includes a printed circuit board, comprising: at least one memory interface buffer chip to connect a memory controller of core logic and an advanced memory buffer (AMB). The memory controller has a memory interface for a parallel memory bus.

    摘要翻译： 用于桥接并行存储器总线和串行存储器总线的存储器接口。 一个实施例包括印刷电路板，包括：用于连接核心逻辑的存储器控​​制器和高级存储器缓冲器（AMB）的至少一个存储器接口缓冲芯片。 存储器控制器具有用于并行存储器总线的存储器接口。

    On-chip supply regulators
    6.
    发明授权
    On-chip supply regulators 有权
    片上电源稳压器

    公开(公告)号：US07366926B2

    公开(公告)日：2008-04-29

    申请号：US11423869

    申请日：2006-06-13

    申请人： Xiaomin Si ,  Howard Yang ,  Stephen Tai

    发明人： Xiaomin Si ,  Howard Yang ,  Stephen Tai

    IPC分类号： G06F1/00

    CPC分类号： G06F1/26

    摘要： Integrated circuit chips with on-chip supply regulators with programmability and initialization. In one embodiment, an integrated circuit, includes: an initialization circuit to assert an initialization signal during powering up of the integrated circuit; a control circuit coupled to the initialization circuit; and a power supply regulator coupled to the control circuit, the power supply regulator to provide a first voltage to the control circuit when the initialization signal is asserted, the power supply regulator to provide a second voltage to the control circuit according to a control signal from the control circuit when the initialization signal is not asserted. In one embodiment, the integrated circuit includes a digital television demodulator.

    摘要翻译： 具有片上电源调节器的集成电路芯片，具有可编程性和初始化功能。 在一个实施例中，集成电路包括：初始化电路，用于在集成电路加电期间断言初始化信号; 耦合到所述初始化电路的控制电路; 以及耦合到所述控制电路的电源调节器，所述电源调节器在所述初始化信号被断言时向所述控制电路提供第一电压，所述电源调节器根据来自所述控制信号的控制信号向所述控制电路提供第二电压 当初始化信号未被置位时，控制电路。 在一个实施例中，集成电路包括数字电视解调器。

    CMOS integrated super-heterodyne television receiver with multiple signal paths
    9.
    发明授权
    CMOS integrated super-heterodyne television receiver with multiple signal paths 有权
    具有多个信号路径的CMOS集成超外差电视接收机

    公开(公告)号：US07639311B2

    公开(公告)日：2009-12-29

    申请号：US11338872

    申请日：2006-01-24

    申请人： Stephen Tai

    发明人： Stephen Tai

    IPC分类号： H04N5/50 ,  H04N5/44

    CPC分类号： H03F3/72 ,  H03F3/189

    摘要： Integrated super-heterodyne television receivers with multiple signal paths implemented using CMOS technology. An integrated circuit, includes: a plurality of CMOS (Complementary Metal-Oxide Semiconductor) low noise amplifiers; an adjustable frequency source; and one or more down-conversion mixers coupled with the adjustable frequency source and the plurality of CMOS low noise amplifiers to form a plurality of super-heterodyne receiving paths between an input to the plurality of CMOS low noise amplifiers and an output from one or more down-conversion mixers; where the integrated circuit is implemented on a single chip of semiconductive substrate.

    摘要翻译： 具有使用CMOS技术实现的多个信号路径的集成超外差电视接收机。 一种集成电路，包括：多个CMOS（互补金属氧化物半导体）低噪声放大器; 可调频源; 以及与可调频率源和多个CMOS低噪声放大器耦合的一个或多个下变频混频器，以在多个CMOS低噪声放大器的输入和来自一个或多个CMOS低噪声放大器的输出之间形成多个超外差接收路径 下转换混频器; 其中集成电路在单芯片半导体衬底上实现。