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    MEMORY INTERFACE TO BRIDGE MEMORY BUSES
    1.
    发明申请
    MEMORY INTERFACE TO BRIDGE MEMORY BUSES 有权
    内存接口到桥接记忆总线

    公开(公告)号：US20070121389A1

    公开(公告)日：2007-05-31

    申请号：US11277650

    申请日：2006-03-28

    申请人： Larry Wu ,  Howard Yang ,  Zhen-Dong Guo ,  Gang Shan ,  Stephen Tai

    发明人： Larry Wu ,  Howard Yang ,  Zhen-Dong Guo ,  Gang Shan ,  Stephen Tai

    IPC分类号： G11C7/10 ,  G06F12/00

    CPC分类号： G11C5/066 ,  G11C5/04 ,  H05K1/181

    摘要： A memory interface to bridge a parallel memory bus and a serial memory bus. One embodiment includes a printed circuit board, comprising: at least one memory interface buffer chip to connect a memory controller of core logic and an advanced memory buffer (AMB). The memory controller has a memory interface for a parallel memory bus.

    摘要翻译： 用于桥接并行存储器总线和串行存储器总线的存储器接口。 一个实施例包括印刷电路板，包括：用于连接核心逻辑的存储器控​​制器和高级存储器缓冲器（AMB）的至少一个存储器接口缓冲芯片。 存储器控制器具有用于并行存储器总线的存储器接口。

    Method for generating read enable signal and memory system using the method
    2.
    发明授权
    Method for generating read enable signal and memory system using the method 有权
    使用该方法生成读启动信号和存储系统的方法

    公开(公告)号：US07983100B2

    公开(公告)日：2011-07-19

    申请号：US12544602

    申请日：2009-08-20

    申请人： Gang Shan ,  Larry Wu

    发明人： Gang Shan ,  Larry Wu

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1051 ,  G11C7/1066

    摘要： A method for generating a read enable signal which is for controlling reading of a pair of data strobe signals and a data signal in a memory system is provided. The method comprises: detecting whether the pair of data strobe signals are both high or low; and generating the read enable signal if the pair of data strobe signals are detected being both high or low. Because the read enable signal is generated using the pair of strobe signals, DLL can be turned off, thus the power consumption of the memory system can be reduced. In addition, the read enable signal is self-aligned with a certain point of the pair of strobe signals, this may enhance precision of the transmission of the pair of strobe signals and the data signal.

    摘要翻译： 提供了一种用于产生读使能信号的方法，用于控制一对数据选通信号的读取和存储系统中的数据信号。 该方法包括：检测一对数据选通信号是高还是低; 以及如果检测到所述一对数据选通信号为高或低，则产生所述读使能信号。 由于读使能信号是使用一对选通信号产生的，所以可以关闭DLL，从而能够降低存储器系统的功耗。 此外，读使能信号与一对选通信号的某一点自对准，这可以提高一对选通信号和数据信号的传输精度。

    Systems and methods for the distribution of differential clock signals to a plurality of low impedance receivers
    4.
    发明授权
    Systems and methods for the distribution of differential clock signals to a plurality of low impedance receivers 有权
    用于将差分时钟信号分配给多个低阻抗接收器的系统和方法

    公开(公告)号：US07558980B2

    公开(公告)日：2009-07-07

    申请号：US11619958

    申请日：2007-01-04

    申请人： Swee Ann Teo ,  Xiaomin Si ,  Larry Wu

    发明人： Swee Ann Teo ,  Xiaomin Si ,  Larry Wu

    IPC分类号： G06F1/00 ,  H04L7/00 ,  G06F1/12

    CPC分类号： H04L25/0272 ,  G06F1/10

    摘要： Systems and methods to distribute clock signals using a common bus. In one embodiment, a clock signal distribution system includes: a bus; a transmitter coupled to the bus to drive a clock signal onto the bus; and one or more receivers coupled to the bus to receive the clock signal, in which the impedance of each receiver is lower than 1000 ohms (or 500 or 200 ohms). In one embodiment, the clock distribution system is on an integrated circuit to distribute the clock on the integrated circuit chip. In one embodiment, the receivers are self-biased; a bias current of the transmitter is a dynamic sum of bias currents of the receivers; and, each of the receivers has a duty cycle correction mechanism. In one embodiment, there is no inductor between the transmitter and the low impedance receiver in the clock distribution system; and the bus has no terminator.

    摘要翻译： 使用公共总线分配时钟信号的系统和方法。 在一个实施例中，时钟信号分配系统包括：总线; 耦合到总线的发射器，以将时钟信号驱动到总线上; 以及耦合到总线以接收时钟信号的一个或多个接收器，其中每个接收机的阻抗低于1000欧姆（或500或200欧姆）。 在一个实施例中，时钟分配系统在集成电路上以将时钟分配在集成电路芯片上。 在一个实施例中，接收器是自偏置的; 发射机的偏置电流是接收机的偏置电流的动态和; 并且每个接收器具有占空比校正机构。 在一个实施例中，时钟分配系统中的发射机和低阻抗接收机之间没有电感器; 而公共汽车没有终点。

    Memory interface to bridge memory buses
    5.
    发明授权
    Memory interface to bridge memory buses 有权
    内存接口桥接内存总线

    公开(公告)号：US07558124B2

    公开(公告)日：2009-07-07

    申请号：US11277650

    申请日：2006-03-28

    申请人： Larry Wu ,  Gang Shan ,  Stephen Tai ,  Howard Yang ,  Zhen-Dong Guo

    发明人： Larry Wu ,  Gang Shan ,  Stephen Tai ,  Howard Yang ,  Zhen-Dong Guo

    IPC分类号： G11C7/10

    CPC分类号： G11C5/066 ,  G11C5/04 ,  H05K1/181

    摘要： A memory interface to bridge a parallel memory bus and a serial memory bus. A printed circuit board includes at least one memory interface buffer chip to connect a memory controller of core logic and an advanced memory buffer (AMB). The memory controller has a memory interface for a parallel memory bus.

    摘要翻译： 用于桥接并行存储器总线和串行存储器总线的存储器接口。 印刷电路板包括至少一个用于连接核心逻辑的存储器控​​制器和高级存储器缓冲器（AMB）的存储器接口缓冲器芯片。 存储器控制器具有用于并行存储器总线的存储器接口。

    Calibration of Read/Write Memory Access via Advanced Memory Buffer
    6.
    发明申请
    Calibration of Read/Write Memory Access via Advanced Memory Buffer 有权
    通过高级内存缓冲区校准读/写存储器访问

    公开(公告)号：US20080256282A1

    公开(公告)日：2008-10-16

    申请号：US11735915

    申请日：2007-04-16

    申请人： Zhendong Guo ,  Larry Wu ,  Xiaorong Ye ,  Gang Shan

    发明人： Zhendong Guo ,  Larry Wu ,  Xiaorong Ye ,  Gang Shan

    IPC分类号： G06F13/14 ,  G06F12/00

    CPC分类号： G06F13/4239

    摘要： Methods and apparatuses to calibrate read/write memory accesses through data buses of different lengths via advanced memory buffers. One embodiment includes an advanced memory buffer (AMB) having: a plurality of ports to interface respectively with a plurality of data buses; a port to interface with a common clock bus for the plurality of data buses; and an adjustable circuit coupled with the plurality of ports to level delays on the plurality of data buses. In one embodiment, the data buses have different wire lengths between the dynamic random access memory (DRAM) memory chips and the advanced memory buffer (AMB).

    摘要翻译： 通过高级存储器缓冲器校准不同长度的数据总线的读/写存储器访问的方法和装置。 一个实施例包括具有以下功能的高级存储器缓冲器（AMB）：多个端口，分别与多个数据总线接口; 与所述多个数据总线的公共时钟总线相连接的端口; 以及与所述多个端口耦合的可调节电路以在所述多个数据总线上的电平延迟。 在一个实施例中，数据总线在动态随机存取存储器（DRAM）存储器芯片和高级存储器缓冲器（AMB）之间具有不同的导线长度。

    Clock and Data Recovery
    7.
    发明申请
    Clock and Data Recovery 有权
    时钟和数据恢复

    公开(公告)号：US20080056426A1

    公开(公告)日：2008-03-06

    申请号：US11468787

    申请日：2006-08-31

    申请人： Xiaomin Si ,  Larry Wu

    发明人： Xiaomin Si ,  Larry Wu

    IPC分类号： H03D3/24

    CPC分类号： H04L7/0337 ,  H03L7/0814 ,  H04L7/0004 ,  H04L7/0041

    摘要： A data and clock recovery circuit having a retimer mode and a resync mode. In one embodiment, a receiver circuit includes: a retimer; a clock recovery circuit to provide a clock signal to the retimer; and an adjustable delay to provide a delayed version of an input signal to the retimer. When in a resync mode, the adjustable delay causes a pre-selected delay in the input signal and the clock recovery circuit dynamically selects a clock phase to generate the clock signal. When in a second mode, the adjustable delay dynamically adjusts the delayed version of the input signal and the clock recovery circuit outputs the clock signal having a pre-selected clock phase.

    摘要翻译： 一种具有重定时器模式和重新同步模式的数据和时钟恢复电路。 在一个实施例中，接收机电路包括：重定时器; 时钟恢复电路，用于向重定时器提供时钟信号; 以及可调延迟，以向延迟器提供输入信号的延迟版本。 当处于重新同步模式时，可调节延迟导致输入信号中预先选择的延迟，并且时钟恢复电路动态地选择时钟相位以产生时钟信号。 当处于第二模式时，可调延迟动态地调节输入信号的延迟版本，并且时钟恢复电路输出具有预选时钟相位的时钟信号。

    METHOD FOR GENERATING READ ENABLE SIGNAL AND MEMORY SYSTEM USING THE METHOD
    9.
    发明申请
    METHOD FOR GENERATING READ ENABLE SIGNAL AND MEMORY SYSTEM USING THE METHOD 有权
    使用该方法生成读启用信号和存储器系统的方法

    公开(公告)号：US20110007585A1

    公开(公告)日：2011-01-13

    申请号：US12544602

    申请日：2009-08-20

    申请人： Gang Shan ,  Larry Wu

    发明人： Gang Shan ,  Larry Wu

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1051 ,  G11C7/1066

    摘要： A method for generating a read enable signal which is for controlling reading of a pair of data strobe signals and a data signal in a memory system is provided. The method comprises: detecting whether the pair of data strobe signals are both high or low; and generating the read enable signal if the pair of data strobe signals are detected being both high or low. Because the read enable signal is generated using the pair of strobe signals, DLL can be turned off, thus the power consumption of the memory system can be reduced. In addition, the read enable signal is self-aligned with a certain point of the pair of strobe signals, this may enhance precision of the transmission of the pair of strobe signals and the data signal.

    摘要翻译： 提供了一种用于产生读使能信号的方法，用于控制一对数据选通信号的读取和存储系统中的数据信号。 该方法包括：检测一对数据选通信号是高还是低; 以及如果检测到所述一对数据选通信号为高或低，则产生所述读使能信号。 由于读使能信号是使用一对选通信号产生的，所以可以关闭DLL，从而能够降低存储器系统的功耗。 此外，读使能信号与一对选通信号的某一点自对准，这可以提高一对选通信号和数据信号的传输精度。

    Calibration of read/write memory access via advanced memory buffer
    10.
    发明授权
    Calibration of read/write memory access via advanced memory buffer 有权
    通过高级内存缓冲区校准读/写存储器访问

    公开(公告)号：US07865660B2

    公开(公告)日：2011-01-04

    申请号：US11735915

    申请日：2007-04-16

    申请人： Zhendong Guo ,  Larry Wu ,  Xiaorong Ye ,  Gang Shan

    发明人： Zhendong Guo ,  Larry Wu ,  Xiaorong Ye ,  Gang Shan

    IPC分类号： G06F12/00 ,  H03L7/06 ,  H03L7/00 ,  G11C7/10 ,  G11C7/00 ,  G01R13/00 ,  G01R35/00 ,  G01R25/00 ,  G01D18/00

    CPC分类号： G06F13/4239

    摘要： Methods and apparatuses to calibrate read/write memory accesses through data buses of different lengths via advanced memory buffers. One embodiment includes an advanced memory buffer (AMB) having: a plurality of ports to interface respectively with a plurality of data buses; a port to interface with a common clock bus for the plurality of data buses; and an adjustable circuit coupled with the plurality of ports to level delays on the plurality of data buses. In one embodiment, the data buses have different wire lengths between the dynamic random access memory (DRAM) memory chips and the advanced memory buffer (AMB).

    摘要翻译： 通过高级存储器缓冲器校准不同长度的数据总线的读/写存储器访问的方法和装置。 一个实施例包括具有以下功能的高级存储器缓冲器（AMB）：多个端口，分别与多个数据总线接口; 与所述多个数据总线的公共时钟总线相连接的端口; 以及与所述多个端口耦合的可调节电路以在所述多个数据总线上的电平延迟。 在一个实施例中，数据总线在动态随机存取存储器（DRAM）存储器芯片和高级存储器缓冲器（AMB）之间具有不同的导线长度。