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公开(公告)号：US20140258685A1
公开(公告)日：2014-09-11
申请号：US13992856
申请日：2011-12-30
Applicant: Srihari Makineni , Steven R. King , Alexander Redkin , Joshua B. Fryman , Ravishankar Iyer , Pavel S. Smirnov , Dmitry Gusev , Dmitri Pavlov
Inventor： Srihari Makineni , Steven R. King , Alexander Redkin , Joshua B. Fryman , Ravishankar Iyer , Pavel S. Smirnov , Dmitry Gusev , Dmitri Pavlov
IPC: G06F9/30
CPC classification number: G06F9/30145 , G06F1/3234 , G06F9/30181 , G06F9/30196 , G06F9/3891
Abstract: A processor may be built with cores that only execute some partial set of the instructions needed to be fully backwards compliant. Thus, in some embodiments power consumption may be reduced by providing partial cores that only execute certain instructions and not other instructions. The instructions not supported may be handled in other, more energy efficient ways, so that, the overall processor, including the partial core, may be fully backwards compliant.
Abstract translation: 处理器可以用仅执行需要完全向后兼容的一些部分指令集的核来构建。 因此，在一些实施例中，可以通过提供仅执行特定指令而不是其他指令的部分核来降低功耗。 不支持的指令可以以其他更节能的方式处理，使得包括部分核心的整体处理器可以完全向后兼容。
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公开(公告)号：US20140146675A1
公开(公告)日：2014-05-29
申请号：US14167533
申请日：2014-01-29
Applicant: Mazhar I. Memon , Steven R. King
Inventor： Mazhar I. Memon , Steven R. King
IPC: H04L12/863 , H04L12/859
CPC classification number: H04L47/24 , H04L47/10 , H04L47/2433 , H04L47/2475 , H04L47/2483 , H04L47/32 , H04L47/50 , H04L47/6255 , H04L47/627 , H04L49/109
Abstract: In an embodiment, an apparatus is provided that may include an integrated circuit including switch circuitry to determine, at least in part, an action to be executed involving a packet. This determination may be based, at least in part, upon flow information determined, at least in part, from the packet, and packet processing policy information. The circuitry may examine the policy information to determine whether a previously-established packet processing policy has been established that corresponds, at least in part, to the flow information. If the circuitry determines, at least in part, that the policy has not been established and the packet is a first packet in a flow corresponding at least in part to the flow information, the switch circuitry may request that at least one switch control program module establish, at least in part, a new packet processing policy corresponding, at least in part, to the flow information.
Abstract translation: 在一个实施例中，提供了一种装置，其可以包括集成电路，其包括开关电路，用于至少部分地确定涉及分组的要执行的动作。 该确定可以至少部分地基于至少部分地从分组确定的流信息和分组处理策略信息。 电路可以检查策略信息以确定是否建立了至少部分地对应于流信息的先前建立的分组处理策略。 如果电路至少部分地确定策略尚未建立并且分组是至少部分地对应于流信息的流中的第一分组，则开关电路可以请求至少一个开关控制程序模块 至少部分地建立至少部分地对应于流信息的新分组处理策略。
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公开(公告)号：US08675491B2
公开(公告)日：2014-03-18
申请号：US13222756
申请日：2011-08-31
Applicant: Mazhar I. Memon , Steven R. King
Inventor： Mazhar I. Memon , Steven R. King
CPC classification number: H04L47/24 , H04L47/10 , H04L47/2433 , H04L47/2475 , H04L47/2483 , H04L47/32 , H04L47/50 , H04L47/6255 , H04L47/627 , H04L49/109
Abstract: In an embodiment, an apparatus is provided that may include an integrated circuit including switch circuitry to determine, at least in part, an action to be executed involving a packet. This determination may be based, at least in part, upon flow information determined, at least in part, from the packet, and packet processing policy information. The circuitry may examine the policy information to determine whether a previously-established packet processing policy has been established that corresponds, at least in part, to the flow information. If the circuitry determines, at least in part, that the policy has not been established and the packet is a first packet in a flow corresponding at least in part to the flow information, the switch circuitry may request that at least one switch control program module establish, at least in part, a new packet processing policy corresponding, at least in part, to the flow information.
Abstract translation: 在一个实施例中，提供了一种装置，其可以包括集成电路，其包括开关电路，用于至少部分地确定涉及分组的要执行的动作。 该确定可以至少部分地基于至少部分地从分组确定的流信息和分组处理策略信息。 电路可以检查策略信息以确定是否建立了至少部分地对应于流信息的先前建立的分组处理策略。 如果电路至少部分地确定策略尚未建立并且分组是至少部分地对应于流信息的流中的第一分组，则开关电路可以请求至少一个开关控制程序模块 至少部分地建立至少部分地对应于流信息的新分组处理策略。
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公开(公告)号：US20130305115A1
公开(公告)日：2013-11-14
申请号：US13940659
申请日：2013-07-12
Applicant: Steven R. KING , Frank L. BERRY , Michael E. KOUNAVIS
Inventor： Steven R. KING , Frank L. BERRY , Michael E. KOUNAVIS
IPC: H03M13/09
CPC classification number: G06F11/1004 , G06F9/30003 , G06F9/30018 , G06F9/30032 , G06F15/76 , G06T1/20 , H03M13/00 , H03M13/09 , H03M13/093 , H03M13/096 , H03M13/157
Abstract: In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed.
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公开(公告)号：US20130305016A1
公开(公告)日：2013-11-14
申请号：US13940665
申请日：2013-07-12
Applicant: Steven R. KING , Frank L. Berry , Michael E. Kounavis
Inventor： Steven R. KING , Frank L. Berry , Michael E. Kounavis
IPC: G06F9/30
CPC classification number: G06F11/1004 , G06F9/30003 , G06F9/30018 , G06F9/30032 , G06F15/76 , G06T1/20 , H03M13/00 , H03M13/09 , H03M13/093 , H03M13/096 , H03M13/157
Abstract: In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed.
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Patent Agency Ranking
公开(公告)号：US08458460B2
公开(公告)日：2013-06-04
申请号：US11863137
申请日：2007-09-27
Applicant: Steven R. King , Erik J. Johnson
Inventor： Steven R. King , Erik J. Johnson
CPC classification number: H04L9/0643 , G06F21/72 , H04L2209/125
Abstract: In general, in one aspect, a computer-implemented method includes determining a digest value based on hash operations on values of, at least, a set op-codes of multiple instructions of a program during execution of the program by a processor.
Abstract translation: 通常，在一个方面，计算机实现的方法包括：基于对由处理器执行程序执行期间的程序的多个指令的至少一组操作码的值，基于散列操作来确定摘要值。
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公开(公告)号：US08156401B2
公开(公告)日：2012-04-10
申请号：US13034993
申请日：2011-02-25
Applicant: Steven R. King , Frank L. Berry , Abhijeet Joglekar
Inventor： Steven R. King , Frank L. Berry , Abhijeet Joglekar
IPC: H03M13/00
CPC classification number: H04L1/0057 , G06F11/1004 , H04L1/005
Abstract: In one embodiment, the present invention includes a method for determining from a data block in a buffer a number of first operands in a first portion of the buffer and a number of second operands in a second portion of the buffer. Based on these numbers, a cyclic redundancy checksum (CRC) operation may be iteratively performed on the first and second operands to obtain a checksum result. The first and second operands are of a different length, and the checksum operation may be executed using processor instructions corresponding to the different lengths. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，本发明包括一种用于从缓冲器中的数据块确定缓冲器的第一部分中的多个第一操作数和缓冲器的第二部分中的多个第二操作数的方法。 基于这些数字，可以对第一和第二操作数迭代地执行循环冗余校验和（CRC）操作，以获得校验和结果。 第一和第二操作数具有不同的长度，并且可以使用对应于不同长度的处理器指令来执行校验和操作。 描述和要求保护其他实施例。
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公开(公告)号：US08031606B2
公开(公告)日：2011-10-04
申请号：US12145236
申请日：2008-06-24
Applicant: Mazhar I. Memon , Steven R. King
Inventor： Mazhar I. Memon , Steven R. King
CPC classification number: H04L47/24 , H04L47/10 , H04L47/2433 , H04L47/2475 , H04L47/2483 , H04L47/32 , H04L47/50 , H04L47/6255 , H04L47/627 , H04L49/109
Abstract: In an embodiment, an apparatus is provided that may include an integrated circuit including switch circuitry to determine, at least in part, an action to be executed involving a packet. This determination may be based, at least in part, upon flow information determined, at least in part, from the packet, and packet processing policy information. The circuitry may examine the policy information to determine whether a previously-established packet processing policy has been established that corresponds, at least in part, to the flow information. If the circuitry determines, at least in part, that the policy has not been established and the packet is a first packet in a flow corresponding at least in part to the flow information, the switch circuitry may request that at least one switch control program module establish, at least in part, a new packet processing policy corresponding, at least in part, to the flow information.
Abstract translation: 在一个实施例中，提供了一种装置，其可以包括集成电路，其包括开关电路，用于至少部分地确定涉及分组的要执行的动作。 该确定可以至少部分地基于至少部分地从分组确定的流信息和分组处理策略信息。 电路可以检查策略信息以确定是否建立了至少部分地对应于流信息的先前建立的分组处理策略。 如果电路至少部分地确定策略尚未建立并且分组是至少部分地对应于流信息的流中的第一分组，则开关电路可以请求至少一个开关控制程序模块 至少部分地建立至少部分地对应于流信息的新分组处理策略。
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9.发明申请公开(公告)号：US20110231744A1
公开(公告)日：2011-09-22
申请号：US13097462
申请日：2011-04-29
Applicant: Steven R. King , Frank Berry , Michael E. Kounavis
Inventor： Steven R. King , Frank Berry , Michael E. Kounavis
CPC classification number: G06F11/1004 , G06F9/30003 , G06F9/30018 , G06F9/30032 , G06F15/76 , G06T1/20 , H03M13/00 , H03M13/09 , H03M13/093 , H03M13/096 , H03M13/157
Abstract: In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，本发明包括一种用于在处理器中接收输入数据并根据用于校验和操作的用户级指令对处理器中的输入数据执行校验和操作的方法。 例如，响应于用户级指令，可以在处理器本身中计算循环冗余校验和。 描述和要求保护其他实施例。
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公开(公告)号：US20110145679A1
公开(公告)日：2011-06-16
申请号：US13034993
申请日：2011-02-25
Applicant: Steven R. King , Frank L. Berry , Abhijeet Joglekar
Inventor： Steven R. King , Frank L. Berry , Abhijeet Joglekar
IPC: H03M13/00
CPC classification number: H04L1/0057 , G06F11/1004 , H04L1/005
Abstract: In one embodiment, the present invention includes a method for determining from a data block in a buffer a number of first operands in a first portion of the buffer and a number of second operands in a second portion of the buffer. Based on these numbers, a cyclic redundancy checksum (CRC) operation may be iteratively performed on the first and second operands to obtain a checksum result. The first and second operands are of a different length, and the checksum operation may be executed using processor instructions corresponding to the different lengths. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，本发明包括一种用于从缓冲器中的数据块确定缓冲器的第一部分中的多个第一操作数和缓冲器的第二部分中的多个第二操作数的方法。 基于这些数字，可以对第一和第二操作数迭代地执行循环冗余校验和（CRC）操作，以获得校验和结果。 第一和第二操作数具有不同的长度，并且可以使用对应于不同长度的处理器指令来执行校验和操作。 描述和要求保护其他实施例。
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