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    Radiation hardened memory cell and design structures
    1.
    发明授权
    Radiation hardened memory cell and design structures 有权
    辐射硬化记忆体和设计结构

    公开(公告)号：US09006827B2

    公开(公告)日：2015-04-14

    申请号：US13292629

    申请日：2011-11-09

    申请人： John G. Massey ,  Scott J. McAllister ,  Charles J. Montrose ,  Stewart E. Rauch, III

    发明人： John G. Massey ,  Scott J. McAllister ,  Charles J. Montrose ,  Stewart E. Rauch, III

    IPC分类号： H01L27/12 ,  H01L21/84 ,  H01L27/11

    CPC分类号： H01L21/84 ,  H01L27/1108 ,  H01L27/1203

    摘要： A radiation hardened static memory cell, methods of manufacture and design structures are provided. The method includes forming one or more first gate stacks and second gate stacks on a substrate. The method further includes providing a shallow implant process for the one or more first gate stacks such that diffusion regions of the one or more first gate stacks are non-butted junction regions. The method further includes providing a deep implant process for the one or more second gates stack such that diffusions regions of the one or more second gate stacks are butted junction regions.

    摘要翻译： 提供了辐射硬化的静电记忆单元，制造方法和设计结构。 该方法包括在衬底上形成一个或多个第一栅极叠层和第二栅极叠层。 该方法还包括为一个或多个第一栅极堆叠提供浅注入工艺，使得一个或多个第一栅极叠层的扩散区域是非对接结的区域。 所述方法还包括为所述一个或多个第二栅极堆叠提供深度注入工艺，使得所述一个或多个第二栅极叠层的扩散区域为对接结区域。

    Methodology for recovery of hot carrier induced degradation in bipolar devices
    5.
    发明授权
    Methodology for recovery of hot carrier induced degradation in bipolar devices 有权
    在双极器件中回收热载体诱导的降解的方法

    公开(公告)号：US07238565B2

    公开(公告)日：2007-07-03

    申请号：US10904985

    申请日：2004-12-08

    申请人： Fernando Guarin ,  J. Edwin Hostetter, Jr. ,  Stewart E. Rauch, III ,  Ping-Chuan Wang ,  Zhijian J. Yang

    发明人： Fernando Guarin ,  J. Edwin Hostetter, Jr. ,  Stewart E. Rauch, III ,  Ping-Chuan Wang ,  Zhijian J. Yang

    IPC分类号： H01L21/8249

    CPC分类号： H01L29/7304 ,  H01L29/7378

    摘要： A method for recovery of degradation caused by avalanche hot carriers is provided that includes subjecting an idle bipolar transistor exhibiting avalanche degradation to a thermal anneal step which increases temperature of the transistor thereby recovering the avalanche degradation of the bipolar transistor. In one embodiment, the annealing source is a self-heating structure that is a Si-containing resistor that is located side by side with an emitter of the bipolar transistor. During the recovering step, the bipolar transistor including the self-heating structure is placed in the idle mode (i.e., without bias) and a current from a separate circuit is flown through the self-heating structure. In another embodiment of the present, the annealing step is a result of providing a high forward current (around the peak fT current or greater) to the bipolar transistor while operating below the avalanche condition (V″CB of less than 1 V). Under the above conditions, about 40% or greater of the degradation can be recovered. In yet another embodiment of the present invention, the thermal annealing step may include a rapid thermal anneal (RTA), a furnace anneal, a laser anneal or a spike anneal.

    摘要翻译： 提供了一种用于回收由雪崩热载体引起的降解的方法，其包括使表现出雪崩降解的空闲双极晶体管经历热退火步骤，所述热退火步骤增加了晶体管的温度，从而恢复了双极晶体管的雪崩劣化。 在一个实施例中，退火源是自发热结构，其是与双极晶体管的发射极并排放置的含Si电阻器。 在恢复步骤期间，包括自发热结构的双极晶体管被置于空闲模式（即，没有偏压），并且来自单独电路的电流流过自热结构。 在本发明的另一个实施例中，退火步骤是在低于雪崩状况（V“CB”）的情况下向双极晶体管提供高正向电流（围绕峰值fT电流或更大）的结果， 小于1V）。 在上述条件下，可以回收约40％以上的降解。 在本发明的又一实施例中，热退火步骤可以包括快速热退火（RTA），炉退火，激光退火或尖峰退火。

    RADIATION HARDENED MEMORY CELL AND DESIGN STRUCTURES
    6.
    发明申请
    RADIATION HARDENED MEMORY CELL AND DESIGN STRUCTURES 有权
    辐射硬化记忆细胞和设计结构

    公开(公告)号：US20130113043A1

    公开(公告)日：2013-05-09

    申请号：US13292629

    申请日：2011-11-09

    申请人： John G. MASSEY ,  Scott J. McALLISTER ,  Charles J. MONTROSE ,  Stewart E. RAUCH, III

    发明人： John G. MASSEY ,  Scott J. McALLISTER ,  Charles J. MONTROSE ,  Stewart E. RAUCH, III

    IPC分类号： H01L27/12 ,  G06F17/50 ,  H01L21/336

    CPC分类号： H01L21/84 ,  H01L27/1108 ,  H01L27/1203

    摘要： A radiation hardened static memory cell, methods of manufacture and design structures are provided. The method includes forming one or more first gate stacks and second gate stacks on a substrate. The method further includes providing a shallow implant process for the one or more first gate stacks such that diffusion regions of the one or more first gate stacks are non-butted junction regions. The method further includes providing a deep implant process for the one or more second gates stack such that diffusions regions of the one or more second gate stacks are butted junction regions.

    摘要翻译： 提供了辐射硬化的静电记忆单元，制造方法和设计结构。 该方法包括在衬底上形成一个或多个第一栅极叠层和第二栅极叠层。 该方法还包括为一个或多个第一栅极堆叠提供浅注入工艺，使得一个或多个第一栅极叠层的扩散区域是非对接结的区域。 所述方法还包括为所述一个或多个第二栅极堆叠提供深度注入工艺，使得所述一个或多个第二栅极叠层的扩散区域为对接结区域。

    Line monitoring of negative bias temperature instabilities by hole injection methods
    7.
    发明授权
    Line monitoring of negative bias temperature instabilities by hole injection methods 失效
    通过空穴注入法线性监测负偏压温度不稳定性

    公开(公告)号：US06521469B1

    公开(公告)日：2003-02-18

    申请号：US09668987

    申请日：2000-09-25

    申请人： Giuseppe La Rosa ,  Fernando J. Guarin ,  Stewart E. Rauch, III

    发明人： Giuseppe La Rosa ,  Fernando J. Guarin ,  Stewart E. Rauch, III

    IPC分类号： H01L2166

    CPC分类号： H01L22/14

    摘要： A process for in-line testing of a metal-oxide-semiconductor field effect transistor (MOSFET) device for negative bias thermal instability (NBTI), which degrades the gate oxide of the MOSFET device. The process generally comprises four steps. First, a hole injection method is selected that produces approximately the same gate oxide degradation as the NBTI under test. Second, a correlation is established between the NBTI degradation and device shifts due to the selected hole injection degradation method. Third, an in-line procedure is developed based on the hole injection method, using the second step to relate the measured shift to NBTI. Finally, a NBTI specification is defined based on the hole injection method using the second step. The MOSFET device is preferably a p-type MOSFET device and the hole injection method is preferably a channel hot-carrier stress method.

    摘要翻译： 用于负偏压热不稳定性（NBTI）的金属氧化物半导体场效应晶体管（MOSFET）器件的在线测试的过程，其降低MOSFET器件的栅极氧化物。 该方法通常包括四个步骤。 首先，选择产生与测试中的NBTI大致相同的栅极氧化物降解的空穴注入方法。 其次，由于所选择的空穴注入降解方法，在NBTI劣化和器件移位之间建立了相关性。 第三，基于空穴注入方法开发了一种在线程序，使用第二步将测量的移位与NBTI相关联。 最后，基于使用第二步骤的空穴注入方法来定义NBTI规范。 MOSFET器件优选为p型MOSFET器件，并且空穴注入法优选为沟道热载流子应力法。

    Methodology for recovery of hot carrier induced degradation in bipolar devices
    8.
    发明授权
    Methodology for recovery of hot carrier induced degradation in bipolar devices 有权
    在双极器件中回收热载体诱导的降解的方法

    公开(公告)号：US07723824B2

    公开(公告)日：2010-05-25

    申请号：US11744621

    申请日：2007-05-04

    申请人： Fernando Guarin ,  J. Edwin Hostetter, Jr. ,  Stewart E. Rauch, III ,  Ping-Chuan Wang ,  Zhijian J. Yang

    发明人： Fernando Guarin ,  J. Edwin Hostetter, Jr. ,  Stewart E. Rauch, III ,  Ping-Chuan Wang ,  Zhijian J. Yang

    IPC分类号： H01L29/73

    CPC分类号： H01L29/7304 ,  H01L29/7378

    摘要： A method for recovery of degradation caused by avalanche hot carriers is provided that includes subjecting an idle bipolar transistor exhibiting avalanche degradation to a thermal anneal step which increases temperature of the transistor thereby recovering the avalanche degradation of the bipolar transistor. In one embodiment, the annealing source is a self-heating structure that is a Si-containing resistor that is located side by side with an emitter of the bipolar transistor. During the recovering step, the bipolar transistor including the self-heating structure is placed in the idle mode (i.e., without bias) and a current from a separate circuit is flown through the self-heating structure. In another embodiment of the present, the annealing step is a result of providing a high forward current (around the peak fT current or greater) to the bipolar transistor while operating below the avalanche condition (VCB of less than 1 V). Under the above conditions, about 40% or greater of the degradation can be recovered. In yet another embodiment of the present invention, the thermal annealing step may include a rapid thermal anneal (RTA), a furnace anneal, a laser anneal or a spike anneal.

    摘要翻译： 提供了一种用于回收由雪崩热载体引起的降解的方法，其包括使表现出雪崩降解的空闲双极晶体管经历热退火步骤，所述热退火步骤增加了晶体管的温度，从而恢复了双极晶体管的雪崩劣化。 在一个实施例中，退火源是自发热结构，其是与双极晶体管的发射极并排放置的含Si电阻器。 在恢复步骤期间，包括自发热结构的双极晶体管被置于空闲模式（即，没有偏压），并且来自单独电路的电流流过自热结构。 在本发明的另一个实施例中，退火步骤是在低于雪崩条件（VCB小于1V）的情况下向双极晶体管提供高正向电流（围绕峰值fT电流或更大）的结果。 在上述条件下，可以回收约40％以上的降解。 在本发明的又一实施例中，热退火步骤可以包括快速热退火（RTA），炉退火，激光退火或尖峰退火。

    Method and structure for in-line monitoring of negative bias temperature instability in field effect transistors
    9.
    发明授权
    Method and structure for in-line monitoring of negative bias temperature instability in field effect transistors 失效
    在线监测场效应晶体管负偏温度不稳定性的方法和结构

    公开(公告)号：US06456104B1

    公开(公告)日：2002-09-24

    申请号：US09377335

    申请日：1999-08-18

    申请人： Fernando J. Guarin ,  Anastasios A. Katsetos ,  Stewart E. Rauch, III

    发明人： Fernando J. Guarin ,  Anastasios A. Katsetos ,  Stewart E. Rauch, III

    IPC分类号： G01R3102

    CPC分类号： G01R31/2621

    摘要： A MOSFET test structure and associated electronics for rapidly heating the MOSFET gate oxide and for applying a stress voltage to the gate. The structure has at least one polysilicon gate with two spaced contacts that permit a heating current to flow through the gate thus rapidly raising the gate temperature to a desired level. External electronics permit applying a measured stress voltage to the gate. The structure is particularly useful in NBTI testing of p-MOSFETs.

    摘要翻译： MOSFET测试结构和相关的电子元件，用于快速加热MOSFET栅极氧化物并向栅极施加应力电压。 该结构具有至少一个多晶硅栅极，其具有两个间隔开的接触，允许加热电流流过栅极，从而将栅极温度快速升高到期望的水平。 外部电子器件允许将测量的应力电压施加到栅极。 该结构在p-MOSFET的NBTI测试中特别有用。