公开(公告)号：US07623390B2

公开(公告)日：2009-11-24

申请号：US12024867

申请日：2008-02-01

申请人： Robert M. Salter, III ,  Kyung Joon Han ,  Sung-Rae Kim ,  Nigel Chan

发明人： Robert M. Salter, III ,  Kyung Joon Han ,  Sung-Rae Kim ,  Nigel Chan

IPC分类号： G11C16/06

CPC分类号： G11C16/3418

摘要： A method for programming a flash memory cell comprises providing input data to the flash cell and providing a segmented programming pulse to the flash memory cell. The segmented programming pulse includes programming segments, each successive programming segment including a programming potential higher than the programming potential used in a previous programming segment, each programming segment followed by a zero-potential compare segment. The output of the flash memory cell is compared with the input data during the compare segment after each programming segment. The segmented programming pulse is terminated if the output of the flash memory cell matches the input data. The programming potential in each programming segment is increased during the programming segment. The programming potential in successive segments is either is increased or stepped up to the final value of the previous programming segment.

摘要翻译： 一种用于对闪存单元进行编程的方法包括向闪存单元提供输入数据，并向闪存单元提供分段编程脉冲。 分段编程脉冲包括编程段，每个连续编程段包括高于先前编程段中使用的编程电位的编程电位，每个编程段后跟零电位比较段。 在每个编程段之后的比较段期间，将闪存单元的输出与输入数据进行比较。 如果闪存单元的输出与输入数据匹配，则分段编程脉冲终止。 在编程段期间，每个编程段中的编程电位增加。 连续段中的编程电位要么增加，要么升高到先前编程段的最终值。

公开(公告)号：US20080137436A1

公开(公告)日：2008-06-12

申请号：US12024867

申请日：2008-02-01

申请人： Robert M. Salter ,  Kyung Joon Han ,  Sung-Rae Kim ,  Nigel Chan

发明人： Robert M. Salter ,  Kyung Joon Han ,  Sung-Rae Kim ,  Nigel Chan

IPC分类号： G11C16/34

CPC分类号： G11C16/3418

摘要： A method for programming a flash memory cell comprises providing input data to the flash cell and providing a segmented programming pulse to the flash memory cell. The segmented programming pulse includes programming segments, each successive programming segment including a programming potential higher than the programming potential used in a previous programming segment, each programming segment followed by a zero-potential compare segment. The output of the flash memory cell is compared with the input data during the compare segment after each programming segment. The segmented programming pulse is terminated if the output of the flash memory cell matches the input data. The programming potential in each programming segment is increased during the programming segment. The programming potential in successive segments is either is increased or stepped up to the final value of the previous programming segment.

摘要翻译： 一种用于对闪存单元进行编程的方法包括向闪存单元提供输入数据，并向闪存单元提供分段编程脉冲。 分段编程脉冲包括编程段，每个连续编程段包括高于先前编程段中使用的编程电位的编程电位，每个编程段后跟零电位比较段。 在每个编程段之后的比较段期间，将闪存单元的输出与输入数据进行比较。 如果闪存单元的输出与输入数据匹配，则分段编程脉冲终止。 在编程段期间，每个编程段中的编程电位增加。 连续段中的编程电位要么增加，要么升高到先前编程段的最终值。

公开(公告)号：US07362610B1

公开(公告)日：2008-04-22

申请号：US11319751

申请日：2005-12-27

申请人： Robert M. Salter, III ,  Kyung Joon Han ,  Sung-Rae Kim ,  Nigel Chan

发明人： Robert M. Salter, III ,  Kyung Joon Han ,  Sung-Rae Kim ,  Nigel Chan

IPC分类号： G11C11/34

CPC分类号： G11C16/3418

摘要： A method for programming a flash memory cell comprises providing input data to the flash cell and providing a segmented programming pulse to the flash memory cell. The segmented programming pulse includes programming segments, each successive programming segment including a programming potential higher than the programming potential used in a previous programming segment, each programming segment followed by a zero-potential compare segment. The output of the flash memory cell is compared with the input data during the compare segment after each programming segment. The segmented programming pulse is terminated if the output of the flash memory cell matches the input data. The programming potential in each programming segment is increased during the programming segment. The programming potential in successive segments is either is increased or stepped up to the final value of the previous programming segment.

摘要翻译： 一种用于对闪存单元进行编程的方法包括向闪存单元提供输入数据，并向闪存单元提供分段编程脉冲。 分段编程脉冲包括编程段，每个连续编程段包括高于先前编程段中使用的编程电位的编程电位，每个编程段后跟零电位比较段。 在每个编程段之后的比较段期间，将闪存单元的输出与输入数据进行比较。 如果闪存单元的输出与输入数据匹配，则分段编程脉冲终止。 在编程段期间，每个编程段中的编程电位增加。 连续段中的编程电位要么增加，要么升高到先前编程段的最终值。

公开(公告)号：US20120170386A1

公开(公告)日：2012-07-05

申请号：US13405523

申请日：2012-02-27

申请人： Thomas Nirschl ,  Nigel Chan ,  Jan Otterstedt

发明人： Thomas Nirschl ,  Nigel Chan ,  Jan Otterstedt

IPC分类号： G11C7/06

CPC分类号： G11C11/5642 ,  G06T7/223 ,  G06T2207/10016 ,  G06T2207/20016 ,  G06T2207/20021 ,  G11C2211/5634 ,  H04N19/53

摘要： Some aspects of the present disclosure relate to a read circuit that uses a hybrid read scheme as set forth herein. In this hybrid read scheme, a state machine, at a first time in the read operation, sets a reference signal SRef to a first reference value to induce determination of a first comparison result. At a second subsequent time in the read operation, the state machine sets the reference signal SRef to a second reference value, which is based on the first comparison result. Setting the reference signal to the second reference value induces determination of a second comparison result. The first and second comparison results are then used to determine the digital value read from the memory cell.

摘要翻译： 本公开的一些方面涉及使用如本文所阐述的混合读取方案的读取电路。 在该混合读取方案中，状态机在读取操作中的第一时间将参考信号SRef设置为第一参考值以引起第一比较结果的确定。 在读取操作的第二随后时间，状态机将参考信号SRef设置为基于第一比较结果的第二参考值。 将参考信号设置为第二参考值引起第二比较结果的确定。 然后使用第一和第二比较结果来确定从存储器单元读取的数字值。

公开(公告)号：US20140050033A1

公开(公告)日：2014-02-20

申请号：US13586136

申请日：2012-08-15

申请人： Michael Otto ,  Nigel Chan

发明人： Michael Otto ,  Nigel Chan

IPC分类号： G11C7/10 ,  G11C7/00

CPC分类号： G11C11/412 ,  G11C11/419

摘要： A memory array assembly and a method for performing a write operation without disturbing data stored in other SRAM cells are provided. The memory array assembly comprises a plurality of SRAM cells, a plurality of avoid-disturb cells, a plurality of sense amplifiers and a plurality of write drivers. The SRAM cells are arranged in rows and columns, wherein each column is coupled to an avoid-disturb cell, a sense amplifier, and a write driver. The avoid-disturb cell receives a select signal capable of assuming first or second states. An output of the sense amplifier is coupled to an input of the write driver when the select signal is in the first state. A data-in bus is coupled to the input of the write driver if the select signal is in the second state. The write driver then sends the output signal to the SRAM cell.

摘要翻译： 提供了存储器阵列组件和用于执行写入操作而不干扰存储在其它SRAM单元中的数据的方法。 存储器阵列组件包括多个SRAM单元，多个避免干扰单元，多个读出放大器和多个写入驱动器。 SRAM单元被排列成行和列，其中每列耦合到避免干扰小区，读出放大器和写入驱动器。 避免干扰小区接收能够采取第一或第二状态的选择信号。 当选择信号处于第一状态时，读出放大器的输出耦合到写入驱动器的输入端。 如果选择信号处于第二状态，则数据输入总线耦合到写入驱动器的输入端。 写驱动器然后将输出信号发送到SRAM单元。

公开(公告)号：US20140050017A1

公开(公告)日：2014-02-20

申请号：US13588327

申请日：2012-08-17

申请人： Michael Otto ,  Nigel Chan

发明人： Michael Otto ,  Nigel Chan

IPC分类号： G11C11/413 ,  G11C5/14

CPC分类号： G11C11/413

摘要： A method comprises writing data to one or more static random access memory (SRAM) cells. Writing data to the one or more SRAM cells comprises applying a first data signal to at least one bit line electrically connected to the one or more SRAM memory cells, electrically disconnecting at least one of a first power supply terminal and a second power supply terminal of each of the one or more SRAM cells from a power supply and applying a word line signal to a word line electrically connected to the one or more SRAM cells. Thereafter, the at least one of the first power supply terminal and the second power supply terminal of each of the one or more SRAM cells is electrically connected to the power source.

摘要翻译： 一种方法包括将数据写入一个或多个静态随机存取存储器（SRAM）单元。 将数据写入到一个或多个SRAM单元包括将第一数据信号施加到电连接到所述一个或多个SRAM存储器单元的至少一个位线，将第一电源端子和第二电源端子中的至少一个电断开， 来自电源的一个或多个SRAM单元中的每一个，并且将字线信号施加到电连接到所述一个或多个SRAM单元的字线。 此后，一个或多个SRAM单元中的每一个的第一电源端子和第二电源端子中的至少一个电连接到电源。

公开(公告)号：US08953388B2

公开(公告)日：2015-02-10

申请号：US13586136

申请日：2012-08-15

申请人： Michael Otto ,  Nigel Chan

发明人： Michael Otto ,  Nigel Chan

IPC分类号： G11C11/419

CPC分类号： G11C11/412 ,  G11C11/419

摘要： A memory array assembly and a method for performing a write operation without disturbing data stored in other SRAM cells are provided. The memory array assembly comprises a plurality of SRAM cells, a plurality of avoid-disturb cells, a plurality of sense amplifiers and a plurality of write drivers. The SRAM cells are arranged in rows and columns, wherein each column is coupled to an avoid-disturb cell, a sense amplifier, and a write driver. The avoid-disturb cell receives a select signal capable of assuming first or second states. An output of the sense amplifier is coupled to an input of the write driver when the select signal is in the first state. A data-in bus is coupled to the input of the write driver if the select signal is in the second state. The write driver then sends the output signal to the SRAM cell.

摘要翻译： 提供了存储器阵列组件和用于执行写入操作而不干扰存储在其它SRAM单元中的数据的方法。 存储器阵列组件包括多个SRAM单元，多个避免干扰单元，多个读出放大器和多个写入驱动器。 SRAM单元被排列成行和列，其中每列耦合到避免干扰小区，读出放大器和写入驱动器。 避免干扰小区接收能够采取第一或第二状态的选择信号。 当选择信号处于第一状态时，读出放大器的输出耦合到写入驱动器的输入。 如果选择信号处于第二状态，则数据输入总线耦合到写入驱动器的输入端。 写驱动器然后将输出信号发送到SRAM单元。

公开(公告)号：US08243520B2

公开(公告)日：2012-08-14

申请号：US12610781

申请日：2009-11-02

申请人： Nigel Chan ,  Wolf Allers ,  Michael Bollu ,  Dimitri Lebedev ,  Jan Otterstedt ,  Christian Peters

发明人： Nigel Chan ,  Wolf Allers ,  Michael Bollu ,  Dimitri Lebedev ,  Jan Otterstedt ,  Christian Peters

IPC分类号： G11C11/34

CPC分类号： G11C16/349 ,  G11C16/0483 ,  G11C16/06

摘要： A method of operating an integrated circuit includes applying at least one first programming pulse to a plurality of non-volatile memory cells to adjust a level of a storage parameter of each of the non-volatile memory cells, the at least one first programming pulse defined by a plurality of pulse parameters each having a fixed valued, and determining a fail count by measuring the number of non-volatile memory cells of the plurality of non-volatile memory cells having a storage parameter level exceeding a verify level. The method further includes determining a change in an programming behavior of the plurality of non-volatile memory cells based on the fail count, adjusting a value of at least one pulse parameter of at least one second programming pulse defined by the plurality of pulse parameters to a desired value based on the change in programming behavior, and applying the at least one second programming pulse to the plurality non-volatile memory cells.

摘要翻译： 操作集成电路的方法包括将至少一个第一编程脉冲施加到多个非易失性存储器单元以调整每个非易失性存储单元的存储参数的电平，所述至少一个第一编程脉冲被定义 通过多个具有固定值的脉冲参数，并且通过测量具有超过验证电平的存储参数电平的多个非易失性存储器单元的非易失性存储器单元的数量来确定故障计数。 该方法还包括基于故障计数确定多个非易失性存储器单元的编程行为的变化，将由多个脉冲参数定义的至少一个第二编程脉冲的至少一个脉冲参数的值调整为 基于编程行为的变化的期望值，以及将所述至少一个第二编程脉冲应用于所述多个非易失性存储器单元。

公开(公告)号：US08817528B2

公开(公告)日：2014-08-26

申请号：US13588327

申请日：2012-08-17

申请人： Michael Otto ,  Nigel Chan

发明人： Michael Otto ,  Nigel Chan

IPC分类号： G11C11/00

CPC分类号： G11C11/413

摘要： A method comprises writing data to one or more static random access memory (SRAM) cells. Writing data to the one or more SRAM cells comprises applying a first data signal to at least one bit line electrically connected to the one or more SRAM memory cells, electrically disconnecting at least one of a first power supply terminal and a second power supply terminal of each of the one or more SRAM cells from a power supply and applying a word line signal to a word line electrically connected to the one or more SRAM cells. Thereafter, the at least one of the first power supply terminal and the second power supply terminal of each of the one or more SRAM cells is electrically connected to the power source.

摘要翻译： 一种方法包括将数据写入一个或多个静态随机存取存储器（SRAM）单元。 将数据写入到一个或多个SRAM单元包括将第一数据信号施加到电连接到所述一个或多个SRAM存储器单元的至少一个位线，将第一电源端子和第二电源端子中的至少一个电断开， 来自电源的一个或多个SRAM单元中的每一个，并且将字线信号施加到电连接到所述一个或多个SRAM单元的字线。 此后，一个或多个SRAM单元中的每一个的第一电源端子和第二电源端子中的至少一个电连接到电源。

公开(公告)号：US08509007B2

公开(公告)日：2013-08-13

申请号：US13405523

申请日：2012-02-27

申请人： Thomas Nirschl ,  Nigel Chan ,  Jan Otterstedt

发明人： Thomas Nirschl ,  Nigel Chan ,  Jan Otterstedt

IPC分类号： G11C7/06 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C11/5642 ,  G06T7/223 ,  G06T2207/10016 ,  G06T2207/20016 ,  G06T2207/20021 ,  G11C2211/5634 ,  H04N19/53

摘要： Some aspects of the present disclosure relate to a read circuit that uses a hybrid read scheme as set forth herein. In this hybrid read scheme, a state machine, at a first time in the read operation, sets a reference signal SRef to a first reference value to induce determination of a first comparison result. At a second subsequent time in the read operation, the state machine sets the reference signal SRef to a second reference value, which is based on the first comparison result. Setting the reference signal to the second reference value induces determination of a second comparison result. The first and second comparison results are then used to determine the digital value read from the memory cell.

摘要翻译： 本公开的一些方面涉及使用如本文所阐述的混合读取方案的读取电路。 在该混合读取方案中，状态机在读取操作中的第一时间将参考信号SRef设置为第一参考值以引起第一比较结果的确定。 在读取操作的第二随后时间，状态机将参考信号SRef设置为基于第一比较结果的第二参考值。 将参考信号设置为第二参考值引起第二比较结果的确定。 然后使用第一和第二比较结果来确定从存储器单元读取的数字值。