公开(公告)号：US06483561B2

公开(公告)日：2002-11-19

申请号：US10059197

申请日：2002-01-31

申请人： Muneo Maruyama ,  Susumu Ohi

发明人： Muneo Maruyama ,  Susumu Ohi

IPC分类号： G02F11335

CPC分类号： G02F1/133504 ,  G02F1/133634

摘要： A liquid crystal display unit produces image carrying light through a liquid crystal layer having a positive anisotropy of refractive index; an optically compensating layer with a negative anisotropy of refractive index is provided on an optical path of the image carrying light so as to compensate the optical anisotropy of the liquid crystal, and the image carrying light is incident onto an optically diffusing layer after the optical compensation so as to widen the viewing angle of the liquid crystal display unit without deterioration of image contrast.

摘要翻译： 液晶显示单元通过具有正折射率各向异性的液晶层产生载影光; 在图像载带光的光路上设置具有负折射率的光学补偿层，以补偿液晶的光学各向异性，并且在光学补偿之后，载像光入射到光漫射层上 以便扩大液晶显示单元的视角而不会降低图像对比度。

公开(公告)号：US5416433A

公开(公告)日：1995-05-16

申请号：US177756

申请日：1994-01-04

申请人： Susumu Ohi

发明人： Susumu Ohi

IPC分类号： H04N9/30 ,  G09G3/18 ,  H03F3/34 ,  H03F3/50 ,  H03K5/003 ,  H03H11/16 ,  H03K19/0175

CPC分类号： H03K5/003

摘要： A data inverting circuit which operates stably at high speed without a negative-feedback loop includes operational amplifier 13 for generating, from inverting reference voltage VREF applied from an external source, a voltage which is twice the inverting reference voltage, and outputting the generated voltage between node N1 and ground line 4. Bipolar transistor Q1 has a base supplied with analog input signal VIN and a collector connected to resistor R6, which is connected to the emitter of transistor Q2 connected as a diode and having a base connected to node N1. The emitter of transistor Q1 is connected to ground line 4 through resistor R7 having the same resistance as resistor R6.

摘要翻译： 在没有负反馈回路的情况下以高速稳定运行的数据反相电路包括运算放大器13，用于从反相参考电压的两倍的电压产生从外部源施加的参考电压VREF，并将产生的电压输出 节点N1和接地线4.双极晶体管Q1具有被提供有模拟输入信号VIN的基极和连接到电阻器R6的集电极，电阻器R6连接到作为二极管连接的晶体管Q2的发射极，并且具有连接到节点N1的基极。 晶体管Q1的发射极通过与电阻R6具有相同电阻的电阻R7连接到地线4。

公开(公告)号：US06657226B1

公开(公告)日：2003-12-02

申请号：US09632247

申请日：2000-08-03

申请人： Naoyuki Taguchi ,  Susumu Ohi

发明人： Naoyuki Taguchi ,  Susumu Ohi

IPC分类号： H01L2900

CPC分类号： H01L27/1244 ,  H01L27/1214

摘要： A high-quality thin-film transistor array. The gate insulating film below the pixel electrode is etched off in its entirely or along a slit extending along a drain bus line in order to simultaneously remove the residual a-Si produced due to defective patterning. The insulating film is interposed between a drain bus line and a pixel electrode to form a boundary separating layer therebetween. The reject ratio is suppressed by reducing the occurrence of point defects of semi-bright spots, ascribable to capacitative coupling to the pixel electrodes as a result of interconnection of the residual a-Si produced by defective patterning to the drain bus line.

摘要翻译： 高品质的薄膜晶体管阵列。 像素电极下方的栅极绝缘膜在其全部或沿着沿着漏极总线延伸的狭缝中被蚀刻掉，以便同时去除由于图案化不良而产生的残余a-Si。 绝缘膜介于漏极总线和像素电极之间，以在它们之间形成边界分离层。 通过由于通过不良图案化产生的残余a-Si与漏极总线的互连，减少了归因于与像素电极的电容耦合的半亮点的点缺陷的发生，从而抑制了拒绝率。

公开(公告)号：US06304305B1

公开(公告)日：2001-10-16

申请号：US09175727

申请日：1998-10-20

申请人： Seiichi Matsumoto ,  Susumu Ohi

发明人： Seiichi Matsumoto ,  Susumu Ohi

IPC分类号： G02F11333

CPC分类号： G02F1/136204 ,  G09G3/3648 ,  G09G2330/08

摘要： An active matrix liquid crystal display has a thin film transistor array which includes scanning lines, signal lines, pixel electrodes, and display thin film transistors. This active matrix liquid crystal display includes, around the image region of the thin film transistor array, a scanning line reference potential line, surge protecting circuits for connecting the scanning lines with the scanning line reference potential line, a signal line reference potential line, and surge protecting circuits for connecting the signal lines with the signal line reference potential line. When a surge voltage is applied to the scanning line or signal line, electric charge is let go to the scanning line reference potential line or signal line reference potential line, respectively. Arbitrary reference potentials can be applied to the scanning line reference potential line and signal line reference potential line. The surge protecting circuit includes two two-terminal thin film transistors.

摘要翻译： 有源矩阵液晶显示器具有包括扫描线，信号线，像素电极和显示薄膜晶体管的薄膜晶体管阵列。 该有源矩阵液晶显示器包括在薄膜晶体管阵列的图像区域周围的扫描线参考电位线，用于将扫描线与扫描线参考电位线连接的浪涌保护电路，信号线参考电位线和 用于将信号线与信号线参考电位线连接的浪涌保护电路。 当浪涌电压施加到扫描线或信号线时，电荷分别放到扫描线参考电位线或信号线参考电位线。 任意参考电位可应用于扫描线参考电位线和信号线参考电位线。 浪涌保护电路包括两个两端子薄膜晶体管。

公开(公告)号：US06226058B1

公开(公告)日：2001-05-01

申请号：US09604017

申请日：2000-06-26

申请人： Susumu Ohi

发明人： Susumu Ohi

IPC分类号： G02F1136

CPC分类号： G02F1/136213 ,  G02F1/134336

摘要： A pixel electrode and a counter electrode of an active matrix liquid crystal display unit are respectively covered with orientation layers differently rubbed, one end portion of the pixel electrode forms an accumulating capacitor together with a gate line and a gate insulating layer inserted therebetween, and the one end portion is varied in width along the gate line so as to confine a disclination line into the liquid crystal over the gate line.

摘要翻译： 有源矩阵液晶显示单元的像素电极和对电极分别被不同地被摩擦的取向层覆盖，像素电极的一个端部与栅极线和插入其间的栅极绝缘层一起形成积聚电容器，并且 一个端部沿着栅极线的宽度变化，从而将旋转线限制在栅极线上的液晶中。

公开(公告)号：US6121632A

公开(公告)日：2000-09-19

申请号：US92944

申请日：1998-06-08

申请人： Naoyuki Taguchi ,  Susumu Ohi

发明人： Naoyuki Taguchi ,  Susumu Ohi

IPC分类号： G02F1/1343 ,  G02F1/136 ,  G02F1/1368 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L29/00

CPC分类号： H01L27/1214

摘要： A high-quality thin-film transistor array. The gate insulating film below the pixel electrode is etched off in its entirely or along a slit extending along a drain bus line in order to simultaneously remove the residual a-Si produced due to defective patterning. The insulating film is interposed between a drain bus line and a pixel electrode to form a boundary separating layer therebetween. The reject ratio is suppressed by reducing the occurrence of point defects of semi-bright spots, ascribable to capacitative coupling to the pixel electrodes as a result of interconnection of the residual a-Si produced by defective patterning to the drain bus line.

公开(公告)号：US5789761A

公开(公告)日：1998-08-04

申请号：US645816

申请日：1996-05-14

申请人： Hirofumi Ihara ,  Kohji Nakashima ,  Susumu Ohi ,  Shin Koide

发明人： Hirofumi Ihara ,  Kohji Nakashima ,  Susumu Ohi ,  Shin Koide

IPC分类号： G02B5/20 ,  G02B1/11 ,  G02B1/113 ,  G02F1/1335 ,  G02F1/136 ,  G02F1/1362 ,  G02F1/1368 ,  G09G3/36 ,  H01L21/336 ,  H01L29/786 ,  G02F1/1343 ,  H01L29/04 ,  H01L37/036

CPC分类号： H01L29/78633 ,  G02F1/136209 ,  G02F1/133502 ,  G02F1/133512 ,  G02F1/1368

摘要： A thin-film transistor (TFT) array for preventing the light reflected inside a liquid crystal panel from entering a channel layer, while suppressing an increase of stray capacitance. A light shading film and an antireflection film atop source and drain electrodes are made of semiconductor layers and are spaced from each other on a TFT. The reduction in reflected light prevents an increase in an off current and therefore improves the quality of a liquid crystal display.

摘要翻译： 一种薄膜晶体管（TFT）阵列，用于防止在液晶面板内反射的光进入沟道层，同时抑制杂散电容的增加。 源极和漏极顶部的遮光膜和抗反射膜由半导体层制成并且在TFT上彼此间隔开。 反射光的减少防止了截止电流的增加，从而提高了液晶显示器的质量。

公开(公告)号：US5726727A

公开(公告)日：1998-03-10

申请号：US625189

申请日：1996-04-01

申请人： Hideo Shibahara ,  Susumu Ohi ,  Muneo Maruyama ,  Michiaki Sakamoto

发明人： Hideo Shibahara ,  Susumu Ohi ,  Muneo Maruyama ,  Michiaki Sakamoto

IPC分类号： G02F1/1333 ,  G02F1/1337 ,  G02F1/1343 ,  G02F1/136 ,  G02F1/1368

CPC分类号： G02F1/134336 ,  G02F1/1368 ,  G02F2001/13373

摘要： In a liquid crystal display device including first and second substrate members, a layer of a liquid crystal material between the first and the second substrate members, an active switching element formed on the first substrate member, a pixel electrode connected to the active switching element and which has first and second portions, a primary signal line connected to the pixel electrode, a secondary signal line adjacent to the primary signal line with the pixel electrode interposed therebetween, a scanning line connected to the pixel electrode, the first portion of the pixel electrode is nearer to the primary signal line than to the secondary signal line while the second portion of the pixel electrode is nearer to the secondary signal line than to the primary signal line.

摘要翻译： 在包括第一和第二基板构件的液晶显示装置中，在第一和第二基板构件之间的液晶材料层，形成在第一基板构件上的有源开关元件，连接到有源开关元件的像素电极和 其具有第一和第二部分，连接到像素电极的主信号线，与主要信号线相邻的辅助信号线，其间插入像素电极，连接到像素电极的扫描线，像素电极的第一部分 比第二信号线更靠近主信号线，而像素电极的第二部分比第一信号线更靠近辅信号线。

公开(公告)号：US5467043A

公开(公告)日：1995-11-14

申请号：US189743

申请日：1994-02-01

申请人： Susumu Ohi

发明人： Susumu Ohi

IPC分类号： G02F1/133 ,  G09G3/18 ,  G09G3/36 ,  G09G5/02 ,  G09G5/10 ,  H04N5/66 ,  H04N9/30 ,  H03L5/00

CPC分类号： G09G3/3607 ,  H04N5/66

摘要： A signal level converting circuit includes an input terminal supplied with an input signal, a reference terminal supplied with a reference voltage, a differential circuit having a first input node, a second input node and an output node, a first level-shift circuit including a first emitter-follower transistor and coupled between the input terminal and the first input node of the differential circuit to level-shift the input signal and supply a level-shifted signal to the first input node, and a second level-shift circuit including a second emitter-follower transistor and coupled between the reference terminal and the second input node of the differential circuit to level-shift the reference voltage and supply a level shifted reference voltage to the second input node.

摘要翻译： 一个信号电平转换电路包括一个输入端，它被提供有一个输入信号，一个被提供参考电压的基准端，一个具有第一输入节点的差分电路，一个第二输入节点和一个输出节点，第一电平移位电路包括 第一发射极跟随器晶体管，并且耦合在差分电路的输入端和第一输入节点之间，以对输入信号进行电平移位，并将电平移位信号提供给第一输入节点;以及第二电平移位电路， 射极跟随器晶体管，并且耦合在差分电路的参考端和第二输入节点之间，以对参考电压进行电平移位，并将电平移动的参考电压提供给第二输入节点。

公开(公告)号：US4963957A

公开(公告)日：1990-10-16

申请号：US250670

申请日：1988-09-29

申请人： Susumu Ohi ,  Masahiko Nakamae ,  Hiroshi Shiba

发明人： Susumu Ohi ,  Masahiko Nakamae ,  Hiroshi Shiba

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/74 ,  H01L21/76 ,  H01L29/417 ,  H01L29/423 ,  H01L29/732

CPC分类号： H01L29/66272 ,  H01L21/743 ,  H01L29/41708 ,  H01L29/42304

摘要： A semiconductor device having a bipolar transistor with a trench is disclosed. An active region of the substrate is surrounded by the trench. Collector, base and emitter regions of the transistor are formed in the active region. A collector electrode is formed in a lower section of the trench, and a base electrode is formed in an upper section of the identical trench.