公开(公告)号：US07079610B1

公开(公告)日：2006-07-18

申请号：US09700617

申请日：1999-05-11

申请人： Magnus Johansson ,  Lennart Olsson ,  Gunnar Bahlenberg ,  Daniel Bengtsson ,  Mikael Isaksson ,  Sven-Rune Olofsson ,  Sven-Göran Ökvist

发明人： Magnus Johansson ,  Lennart Olsson ,  Gunnar Bahlenberg ,  Daniel Bengtsson ,  Mikael Isaksson ,  Sven-Rune Olofsson ,  Sven-Göran Ökvist

IPC分类号： H04B1/10

CPC分类号： H04L25/03159 ,  H04L27/2655 ,  H04L2025/03414 ,  H04L2025/03522 ,  H04L2025/03617

摘要： In a multi-carrier system employing OFDM, for example DMT, an adaptive channel equalizer is normally used, operating in the frequency domain. The sampling clock is controlled so that the time delay between the transmitter and the receiver is effectively eliminated. If the information used to control the sampling clock is received from the equalized data stream, it will introduce an ambiguity between the operation of the channel equalizer and the mechanism used to control the sampling clock. Operation of the equalizer can mask an increasing time difference, between transmitter and receiver, which the sample clock controller should be tracking. The present invention eliminates the ambiguities in the operation of the equalizer and sample clock controller by preventing the equalizer from accepting time differences which should be corrected by operation of the sample clock controller.

摘要翻译： 在采用OFDM的多载波系统中，例如DMT，通常使用自适应信道均衡器，在频域中工作。 控制采样时钟，以便有效地消除发射机和接收机之间的时间延迟。 如果从均衡数据流接收到用于控制采样时钟的信息，则会在通道均衡器的操作和用于控制采样时钟的机制之间引入歧义。 均衡器的操作可以掩盖采样时钟控制器应该跟踪的发射机和接收机之间的增加的时间差。 本发明通过防止均衡器接受应该通过采样时钟控制器的操作来校正的时间差来消除均衡器和采样时钟控制器的操作中的模糊性。

公开(公告)号：US06606047B1

公开(公告)日：2003-08-12

申请号：US09700888

申请日：2000-11-20

申请人： Per Ola Börjesson ,  Mikael Isaksson ,  Per Ödling ,  Daniel Bengtsson ,  Gunnar Bahlenberg ,  Magnus Johansson ,  Lennart Olsson ,  Sven Göran Ökvist

发明人： Per Ola Börjesson ,  Mikael Isaksson ,  Per Ödling ,  Daniel Bengtsson ,  Gunnar Bahlenberg ,  Magnus Johansson ,  Lennart Olsson ,  Sven Göran Ökvist

IPC分类号： H03M112

CPC分类号： H03M1/12

摘要： A circuit, for digitizing an analogue signal includes an analogue to digital converter, a clip processor adapted to estimate a value for clipped digital signal samples, and a buffer adapted to dynamically store a plurality of digitized samples produced by the analogue to digital converter. The clip processor is adapted to read digitized samples from the buffer and replace clipped digitized samples with the estimated values, thereby mitigating the effects of clipping in an output of the circuit.

摘要翻译： 用于数字化模拟信号的电路包括模数转换器，适于估计经裁剪的数字信号样本的值的剪辑处理器，以及适于动态地存储由模数转换器产生的多个数字化采样的缓冲器。 剪辑处理器适于从缓冲器读取数字化样本，并用估计值替换剪切的数字化样本，从而减轻限幅在电路输出中的影响。

公开(公告)号：US07050489B1

公开(公告)日：2006-05-23

申请号：US09856438

申请日：1999-11-18

申请人： Frank Sjöberg ,  Sarah Kate Wilson ,  Rickard Nilsson ,  Daniel Bengtsson ,  Mikael Isaksson ,  Tomas Nordström ,  Per Ödling ,  Gunnar Bahlenberg ,  Magnus Johansson ,  Lennart Olsson ,  Sven-Göran Ökvist

发明人： Frank Sjöberg ,  Sarah Kate Wilson ,  Rickard Nilsson ,  Daniel Bengtsson ,  Mikael Isaksson ,  Tomas Nordström ,  Per Ödling ,  Gunnar Bahlenberg ,  Magnus Johansson ,  Lennart Olsson ,  Sven-Göran Ökvist

IPC分类号： H04B1/38

CPC分类号： H04B3/32 ,  H04L5/0007

摘要： One problem, frequently encountered with VDSL transmission systems, is that upstream FEXT produced by system users having short wires can be very strong. Users having shorter wires get high bit rates whereas users having longer wires get low bit rates. In extreme cases it may happen that users with wire lengths greater than 1000 meter cannot transmit data upstream. The present invention provides a VDST transmission system with a plurality of modems. The modems are located at varying distances from a central station. There is a target bit rate for each modem. That modems on shorter wires have control means for reducing their transmit power. This reduces the FEXT produced by these modems enabling modems on longer wires to transmit at higher bit rates.

摘要翻译： VDSL传输系统经常遇到的一个问题是系统用户短路导致的上游FEXT可能非常强大。 具有较短导线的用户获得高比特率，而具有较长导线的用户可获得较低的比特率。 在极端情况下，线长大于1000米的用户无法向上传输数据。 本发明提供一种具有多个调制解调器的VDST传输系统。 调制解调器位于距离中心站不同的距离。 每个调制解调器有一个目标比特率。 较短导线上的调制解调器具有降低发射功率的控制装置。 这减少了由这些调制解调器产生的FEXT，使得更长导线上的调制解调器能够以更高的比特率传输。