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公开(公告)号：US07440350B2
公开(公告)日：2008-10-21
申请号：US11708348
申请日：2007-02-21
CPC分类号： G11C7/12 , G11C2207/005 , H01L27/105 , H01L27/10897
摘要： A DRAM whose operation is sped up and power consumption is reduced is provided. A pair of precharge MOSFETs for supplying a precharge voltage to a pair of input/output nodes of a CMOS sense amplifier is provided; the pair of input/output nodes are connected to a complementary bit-line pair via a selection switch MOSFET; a first equalize MOSFET is provided between the complementary bit-line pair for equalizing them; a memory cell is provided between one of the complementary bit-line pair and a word line intersecting with it; gate insulators of the selection switch MOSFETs and first equalize MOSFET are formed by first film thickness; a gate insulator of the precharge MOSFET is formed by second film thickness thinner than the first film thickness; a precharge signal corresponding to a power supply voltage is supplied to the precharge MOSFET; and an equalize signal and a selection signal corresponding to a boost voltage are supplied to the first equalize MOSFET and the selection switch MOSFET, respectively.
摘要翻译： 提供了其操作加快并且功耗降低的DRAM。 提供一对用于向CMOS读出放大器的一对输入/输出节点提供预充电电压的预充电MOSFET; 一对输入/输出节点经由选择开关MOSFET连接到互补位线对; 在互补位线对之间提供第一均衡MOSFET以使它们均衡; 在互补位线对之一和与其相交的字线之间提供存储单元; 选择开关MOSFET和第一均衡MOSFET的栅极绝缘体由第一膜厚度形成; 预充电MOSFET的栅极绝缘体由比第一膜厚度薄的第二膜厚形成; 对应于电源电压的预充电信号被提供给预充电MOSFET; 并且将均衡信号和对应于升压电压的选择信号分别提供给第一均衡MOSFET和选择开关MOSFET。
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公开(公告)号：US07193912B2
公开(公告)日：2007-03-20
申请号：US11136510
申请日：2005-05-25
CPC分类号： G11C7/12 , G11C2207/005 , H01L27/105 , H01L27/10897
摘要： A DRAM whose operation is sped up and power consumption is reduced is provided. A pair of precharge MOSFETs for supplying a precharge voltage to a pair of input/output nodes of a CMOS sense amplifier is provided; the pair of input/output nodes are connected to a complementary bit-line pair via a selection switch MOSFET; a first equalize MOSFET is provided between the complementary bit-line pair for equalizing them; a memory cell is provided between one of the complementary bit-line pair and a word line intersecting with it; gate insulators of the selection switch MOSFETs and first equalize MOSFET are formed by first film thickness; a gate insulator of the precharge MOSFET is formed by second film thickness thinner than the first film thickness; a precharge signal corresponding to a power supply voltage is supplied to the precharge MOSFET; and an equalize signal and a selection signal corresponding to a boost voltage are supplied to the first equalize MOSFET and the selection switch MOSFET, respectively.
摘要翻译： 提供了其操作加快并且功耗降低的DRAM。 提供一对用于向CMOS读出放大器的一对输入/输出节点提供预充电电压的预充电MOSFET; 一对输入/输出节点经由选择开关MOSFET连接到互补位线对; 在互补位线对之间提供第一均衡MOSFET以使它们均衡; 在互补位线对之一和与其相交的字线之间提供存储单元; 选择开关MOSFET和第一均衡MOSFET的栅极绝缘体由第一膜厚度形成; 预充电MOSFET的栅极绝缘体由比第一膜厚度薄的第二膜厚形成; 对应于电源电压的预充电信号被提供给预充电MOSFET; 并且将均衡信号和对应于升压电压的选择信号分别提供给第一均衡MOSFET和选择开关MOSFET。
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公开(公告)号：US20070159901A1
公开(公告)日：2007-07-12
申请号：US11708348
申请日：2007-02-21
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C2207/005 , H01L27/105 , H01L27/10897
摘要： A DRAM whose operation is sped up and power consumption is reduced is provided. A pair of precharge MOSFETs for supplying a precharge voltage to a pair of input/output nodes of a CMOS sense amplifier is provided; the pair of input/output nodes are connected to a complementary bit-line pair via a selection switch MOSFET; a first equalize MOSFET is provided between the complementary bit-line pair for equalizing them; a memory cell is provided between one of the complementary bit-line pair and a word line intersecting with it; gate insulators of the selection switch MOSFETs and first equalize MOSFET are formed by first film thickness; a gate insulator of the precharge MOSFET is formed by second film thickness thinner than the first film thickness; a precharge signal corresponding to a power supply voltage is supplied to the precharge MOSFET; and an equalize signal and a selection signal corresponding to a boost voltage are supplied to the first equalize MOSFET and the selection switch MOSFET, respectively.
摘要翻译： 提供了其操作加快并且功耗降低的DRAM。 提供一对用于向CMOS读出放大器的一对输入/输出节点提供预充电电压的预充电MOSFET; 一对输入/输出节点经由选择开关MOSFET连接到互补位线对; 在互补位线对之间提供第一均衡MOSFET以使它们均衡; 在互补位线对之一和与其相交的字线之间提供存储单元; 选择开关MOSFET和第一均衡MOSFET的栅极绝缘体由第一膜厚度形成; 预充电MOSFET的栅极绝缘体由比第一膜厚度薄的第二膜厚形成; 对应于电源电压的预充电信号被提供给预充电MOSFET; 并且将均衡信号和对应于升压电压的选择信号分别提供给第一均衡MOSFET和选择开关MOSFET。
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公开(公告)号：US20050265096A1
公开(公告)日：2005-12-01
申请号：US11136510
申请日：2005-05-25
IPC分类号： H01L27/108 , G11C7/00 , G11C7/12 , G11C11/401 , G11C11/409 , H01L21/8242 , H01L27/105
CPC分类号： G11C7/12 , G11C2207/005 , H01L27/105 , H01L27/10897
摘要： A DRAM whose operation is sped up and power consumption is reduced is provided. A pair of precharge MOSFETs for supplying a precharge voltage to a pair of input/output nodes of a CMOS sense amplifier is provided; the pair of input/output nodes are connected to a complementary bit-line pair via a selection switch MOSFET; a first equalize MOSFET is provided between the complementary bit-line pair for equalizing them; a memory cell is provided between one of the complementary bit-line pair and a word line intersecting with it; gate insulators of the selection switch MOSFETs and first equalize MOSFET are formed by first film thickness; a gate insulator of the precharge MOSFET is formed by second film thickness thinner than the first film thickness; a precharge signal corresponding to a power supply voltage is supplied to the precharge MOSFET; and an equalize signal and a selection signal corresponding to a boost voltage are supplied to the first equalize MOSFET and the selection switch MOSFET, respectively.
摘要翻译： 提供了其操作加快并且功耗降低的DRAM。 提供一对用于向CMOS读出放大器的一对输入/输出节点提供预充电电压的预充电MOSFET; 一对输入/输出节点经由选择开关MOSFET连接到互补位线对; 在互补位线对之间提供第一均衡MOSFET以使它们均衡; 在互补位线对之一和与其相交的字线之间提供存储单元; 选择开关MOSFET和第一均衡MOSFET的栅极绝缘体由第一膜厚度形成; 预充电MOSFET的栅极绝缘体由比第一膜厚度薄的第二膜厚形成; 对应于电源电压的预充电信号被提供给预充电MOSFET; 并且将均衡信号和对应于升压电压的选择信号分别提供给第一均衡MOSFET和选择开关MOSFET。
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