公开(公告)号：US07851376B2

公开(公告)日：2010-12-14

申请号：US12364088

申请日：2009-02-02

申请人： Daewon Yang ,  Woo-Hyeong Lee ,  Tai-chi Su ,  Yun-Yu Wang

发明人： Daewon Yang ,  Woo-Hyeong Lee ,  Tai-chi Su ,  Yun-Yu Wang

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/02274 ,  C23C16/345 ,  C23C16/505 ,  H01L21/0217 ,  H01L21/3185 ,  H01L21/76829 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/7843

摘要： Embodiments of the invention provide a method of forming a compressive stress nitride film overlying a plurality of p-type field effect transistor gate structures produced on a substrate through a high-density plasma deposition process. Embodiments include generating an environment filled with high-density plasma using source gases of at least silane, argon and nitrogen; biasing the substrate to a high frequency power of varying density, in a range between 0.8 W/cm2 and 5.0 W/cm2; and depositing the high-density plasma to the plurality of gate structures to form the compressive stress nitride film.

摘要翻译： 本发明的实施例提供一种通过高密度等离子体沉积工艺形成在衬底上产生的多个p型场效应晶体管栅极结构的压应力氮化物膜的形成方法。 实施例包括使用至少硅烷，氩和氮的源气体产生填充有高密度等离子体的环境; 在0.8W / cm 2至5.0W / cm 2之间的范围内将衬底偏置为变化密度的高频功率; 以及将所述高密度等离子体沉积到所述多个栅极结构以形成所述压应力氮化物膜。

公开(公告)号：US20090176350A1

公开(公告)日：2009-07-09

申请号：US11969272

申请日：2008-01-04

申请人： MICHAEL P. BELYANSKY ,  Brian J. Greene ,  Habib Hichri ,  Tai-Chi Su

发明人： MICHAEL P. BELYANSKY ,  Brian J. Greene ,  Habib Hichri ,  Tai-Chi Su

IPC分类号： H01L21/322

CPC分类号： H01L21/3221 ,  H01L21/265 ,  H01L29/7833

摘要： A method embodiment deposits a first dielectric layer over a transistor and then implants a gettering agent into the first dielectric layer. After this first dielectric layer is formed, the method forms a second (thicker) dielectric layer over the first dielectric layer. After this, the standard contacts are formed through the insulating layer to the source, drain, gate, etc. of the transistor. Additionally, reactive ion etching, chemical mechanical processing, and other back-end-of-line processing are performed. The back-end-of-line processes can introduce mobile ions into the dielectric over a transistor; however, the gettering agent traps the mobile ions and prevents the mobile ions from contaminating the transistor.

摘要翻译： 方法实施例在晶体管上沉积第一介电层，然后将吸气剂注入第一介电层。 在形成第一介电层之后，该方法在第一介电层上形成第二（较厚的）介电层。 之后，通过绝缘层将晶体管的源极，漏极，栅极等形成标准触点。 此外，执行反应离子蚀刻，化学机械处理和其它后端处理。 后端工艺可以通过晶体管将移动离子引入电介质; 然而，吸气剂捕获移动离子并防止移动离子污染晶体管。

公开(公告)号：US20090137109A1

公开(公告)日：2009-05-28

申请号：US12364088

申请日：2009-02-02

申请人： Daewon Yang ,  Woo-Hyeong Lee ,  Tai-chi Su ,  Yun-Yu Wang

发明人： Daewon Yang ,  Woo-Hyeong Lee ,  Tai-chi Su ,  Yun-Yu Wang

IPC分类号： H01L21/71

CPC分类号： H01L21/02274 ,  C23C16/345 ,  C23C16/505 ,  H01L21/0217 ,  H01L21/3185 ,  H01L21/76829 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/7843

摘要： Embodiments of the invention provide a method of forming a compressive stress nitride film overlying a plurality of p-type field effect transistor gate structures produced on a substrate through a high-density plasma deposition process. Embodiments include generating an environment filled with high-density plasma using source gases of at least silane, argon and nitrogen; biasing the substrate to a high frequency power of varying density, in a range between 0.8 W/cm2 and 5.0 W/cm2; and depositing the high-density plasma to the plurality of gate structures to form the compressive stress nitride film.

摘要翻译： 本发明的实施例提供一种通过高密度等离子体沉积工艺形成在衬底上产生的多个p型场效应晶体管栅极结构的压应力氮化物膜的形成方法。 实施例包括使用至少硅烷，氩和氮的源气体产生填充有高密度等离子体的环境; 在0.8W / cm 2至5.0W / cm 2之间的范围内将衬底偏置为变化密度的高频功率; 以及将所述高密度等离子体沉积到所述多个栅极结构以形成所述压应力氮化物膜。

公开(公告)号：US20070269992A1

公开(公告)日：2007-11-22

申请号：US11419217

申请日：2006-05-19

申请人： Daewon Yang ,  Woo-Hyeong Lee ,  Tai-chi Su ,  Yun-Yu Wang

发明人： Daewon Yang ,  Woo-Hyeong Lee ,  Tai-chi Su ,  Yun-Yu Wang

IPC分类号： H01L21/31 ,  H01L21/4763 ,  H01L21/3205

CPC分类号： H01L21/02274 ,  C23C16/345 ,  C23C16/505 ,  H01L21/0217 ,  H01L21/3185 ,  H01L21/76829 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/7843

摘要： Embodiments of the invention provide a method of forming a compressive stress nitride film overlying a plurality of p-type field effect transistor gate structures produced on a substrate through a high-density plasma deposition process. Embodiments include generating an environment filled with high-density plasma using source gases of at least silane, argon and nitrogen; biasing the substrate to a high frequency power of varying density, in a range between 0.8 W/cm2 and 5.0 W/cm2; and depositing the high-density plasma to the plurality of gate structures to form the compressive stress nitride film.

摘要翻译： 本发明的实施例提供一种通过高密度等离子体沉积工艺形成在衬底上产生的多个p型场效应晶体管栅极结构的压应力氮化物膜的形成方法。 实施例包括使用至少硅烷，氩和氮的源气体产生填充有高密度等离子体的环境; 在0.8W / cm 2和5.0W / cm 2之间的范围内将衬底偏置为变化密度的高频功率; 以及将所述高密度等离子体沉积到所述多个栅极结构以形成所述压应力氮化物膜。

公开(公告)号：US07514370B2

公开(公告)日：2009-04-07

申请号：US11419217

申请日：2006-05-19

申请人： Daewon Yang ,  Woo-Hyeong Lee ,  Tai-chi Su ,  Yun-Yu Wang

发明人： Daewon Yang ,  Woo-Hyeong Lee ,  Tai-chi Su ,  Yun-Yu Wang

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/02274 ,  C23C16/345 ,  C23C16/505 ,  H01L21/0217 ,  H01L21/3185 ,  H01L21/76829 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/7843

摘要： Embodiments of the invention provide a method of forming a compressive stress nitride film overlying a plurality of p-type field effect transistor gate structures produced on a substrate through a high-density plasma deposition process. Embodiments include generating an environment filled with high-density plasma using source gases of at least silane, argon and nitrogen; biasing the substrate to a high frequency power of varying density, in a range between 0.8 W/cm2 and 5.0 W/cm2; and depositing the high-density plasma to the plurality of gate structures to form the compressive stress nitride film.

摘要翻译： 本发明的实施例提供一种通过高密度等离子体沉积工艺形成在衬底上产生的多个p型场效应晶体管栅极结构的压应力氮化物膜的形成方法。 实施例包括使用至少硅烷，氩和氮的源气体产生填充有高密度等离子体的环境; 在0.8W / cm 2至5.0W / cm 2之间的范围内将衬底偏置为变化密度的高频功率; 以及将所述高密度等离子体沉积到所述多个栅极结构以形成所述压应力氮化物膜。

公开(公告)号：US06800530B2

公开(公告)日：2004-10-05

申请号：US10342420

申请日：2003-01-14

申请人： Byoung Hun Lee ,  Bachir Dirahoui ,  Effendi Leobandung ,  Tai-Chi Su

发明人： Byoung Hun Lee ,  Bachir Dirahoui ,  Effendi Leobandung ,  Tai-Chi Su

IPC分类号： H01L21336

CPC分类号： H01L29/518 ,  H01L21/823828 ,  H01L29/4966 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628

摘要： An integrated circuit employing CMOS technology employs a process integration that combines a source/drain silicide with a replacement gate process using a triple layer hardmask that is consumed during the course of processing in which a first temporary gate sidewall spacer defines an area for the formation of the raised source and drain and a second temporary spacer defines an area for the implant of the source and drain and for the siliciding of the source and drain while the temporary gate is protected from silicidaiton by the hardmask.

公开(公告)号：US20090176351A1

公开(公告)日：2009-07-09

申请号：US11969280

申请日：2008-01-04

申请人： HUILONG ZHU ,  Tai-chi Su ,  Ying Li

发明人： HUILONG ZHU ,  Tai-chi Su ,  Ying Li

IPC分类号： H01L21/322

CPC分类号： H01L21/265 ,  H01L21/3221 ,  H01L29/7833

摘要： A method embodiment deposits a dielectric layer over a transistor and then implants a gettering agent into the dielectric layer. The insulating layer into which the gettering agent is implanted comprises a single continuous insulating layer and is the insulating layer that borders the next layer of metallization. After this dielectric layer is formed, standard contacts (tungsten) are formed through the insulating layer to the source, drain, gate, etc. of the transistor. Additionally, reactive ion etching of the contacts is performed. The reactive ion etching process can create mobile ions; however, the gettering agent traps the mobile ions and prevents the mobile ions from contaminating the transistor.

摘要翻译： 方法实施例将电介质层沉积在晶体管上，然后将吸杂剂注入电介质层。 吸附剂注入的绝缘层包括单个连续绝缘层，并且是与下一层金属化接触的绝缘层。 在形成该电介质层之后，通过绝缘层到晶体管的源极，漏极，栅极等形成标准触点（钨）。 此外，进行触点的反应离子蚀刻。 反应离子蚀刻工艺可以产生移动离子; 然而，吸气剂捕获移动离子并防止移动离子污染晶体管。