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40 条记录 (耗时 0.029 秒)

    Level adjustment circuit
    1.
    发明授权
    Level adjustment circuit 有权
    电平调节电路

    公开(公告)号：US07110557B2

    公开(公告)日：2006-09-19

    申请号：US09818249

    申请日：2001-03-26

    申请人： Yoshihiko Kon ,  Takashi Uchino ,  Hiroshi Kaneko ,  Takahiko Masumoto

    发明人： Yoshihiko Kon ,  Takashi Uchino ,  Hiroshi Kaneko ,  Takahiko Masumoto

    IPC分类号： H03G3/00

    CPC分类号： H03G3/3089 ,  H03G3/001

    摘要： Volume adjustment is performed in small steps at a DSP (12) and volume adjustment is performed in wide steps at electronic volume circuits (18L, 18R). Adjustment only by the DSP (12) is performed for a small volume range less than or equal to a predetermined level. For a volume higher than or equal to the predetermined level, fine adjustment by the DSP (12) at the transient period of volume adjustment is combined to reduce the increment of variation so that the volume adjustment is performed gradually.

    摘要翻译： 在DSP（12）处以小步骤进行音量调节，并且在电子体积电路（18L，18R）上以宽的步长进行音量调节。 对于小于或等于预定电平的小体积范围，仅对DSP（12）进行调整。 对于高于或等于预定电平的音量，组合音量调节过程中DSP（12）的微调，以减小变化的增量，从而逐渐进行音量调节。

    ELECTRONIC COMPONENT MOUNTING APPARATUS AND ELECTRONIC COMPONENT MOUNTING METHOD
    2.
    发明申请
    ELECTRONIC COMPONENT MOUNTING APPARATUS AND ELECTRONIC COMPONENT MOUNTING METHOD 有权
    电子元件安装设备和电子元件安装方法

    公开(公告)号：US20100229378A1

    公开(公告)日：2010-09-16

    申请号：US12293646

    申请日：2007-03-12

    申请人： Takashi Uchino ,  Tadashi Shinozaki ,  Norifumi Eguchi ,  Naoki Yamauchi ,  Masao Hidaka ,  Toru Nakazono

    发明人： Takashi Uchino ,  Tadashi Shinozaki ,  Norifumi Eguchi ,  Naoki Yamauchi ,  Masao Hidaka ,  Toru Nakazono

    IPC分类号： B23P19/00

    CPC分类号： H05K13/0478 ,  H01L21/67144 ,  H01L24/29 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/97 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/07802 ,  H05K13/085 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/53174 ,  Y10T29/53178 ,  Y10T29/53183 ,  H01L2224/83

    摘要： A challenge to be met by the present invention is to provide an electronic component mounting apparatus and an electronic component mounting method that enable a reduction in the frequency of operation required with switching of a component type, to thus enhance productivity.In component mount operation for taking chips of component types A, B, and C out of a component supply portion by means of a single mount head and mounting the chips on two substrates held by a first lane and a second lane, when a subsequently-carried-in subsequent substrate has come to be able to undergo component mount operation before completion of processing pertaining to a preceding substrate mount process in which component mount operation is carried out on a previously-carried-in preceding substrate among a plurality of substrates, processing pertaining to a subsequent substrate mount process is started by taking, as mount start components, chips already serving as targets of component mount operation for the preceding substrate at this timing, and processing pertaining to the preceding substrate mount process during which mounting is not yet completed is continually carried out. Thereby, the frequency of operation required with switching of a component type, such as replacement of a nozzle, can be reduced.

    摘要翻译： 本发明要解决的课题是提供一种电子部件安装装置和电子部件安装方法，其能够降低部件类型的切换所需的操作频率，从而提高生产率。 在用于通过单个安装头从组件供应部分中取出组件类型A，B和C的芯片的组件安装操作中，并且将芯片安装在由第一通道和第二通道保持的两个基板上， 随后的衬底已经能够在完成与之前的衬底安装工艺相关的处理之前进行组件安装操作，其中在多个衬底之间对先前存在的在前衬底进行组件安装操作，处理 关于随后的基板安装工艺，通过作为安装启动部件开始已经作为前面基板的部件安装操作的目标的芯片，以及与之前的基板安装处理有关的处理，其中安装尚未完成 不断进行 由此，可以减少切换喷嘴等部件的切换所需的操作频率。

    Motor with multiple bus rings
    3.
    发明授权
    Motor with multiple bus rings 有权
    带多个总线环的电机

    公开(公告)号：US07795767B2

    公开(公告)日：2010-09-14

    申请号：US12401834

    申请日：2009-03-11

    申请人： Tetsuji Ueta ,  Hiroaki Sagara ,  Yukifumi Yamaguchi ,  Takashi Uchino ,  Kenji Taguchi

    发明人： Tetsuji Ueta ,  Hiroaki Sagara ,  Yukifumi Yamaguchi ,  Takashi Uchino ,  Kenji Taguchi

    IPC分类号： H02K11/00

    CPC分类号： H02K3/522 ,  H02K1/148 ,  H02K5/225 ,  H02K2203/09 ,  H02K2203/12

    摘要： An aspect of the invention provides a motor that comprises: a stator including multiple motor coils; multiple bus rings configured to distribute currents of different phases to the motor coils; and a ring-shaped bus ring holder in which multiple holding grooves configured to hold the respective bus rings are formed, wherein: each of the motor coils includes an insulator around which a wound wire is wound; the insulator includes an outer flange formed at an outer side of the wound wire in a radial direction of the motor and extending in an axial direction of the motor; and the bus ring holder is arranged at an outer side of the outer flange in the radial direction of the motor, and contiguous to the outer flange.

    摘要翻译： 本发明的一个方面提供了一种电动机，其包括：定子，包括多个电动机线圈; 多个总线环配置成将不同相的电流分配到电动机线圈; 以及环形总线环保持器，其中形成有用于保持各个总线环的多个保持槽，其中：每个电动机线圈包括缠绕有绕线的绝缘体; 所述绝缘体包括沿所述绕线的外侧形成在所述电动机的径向方向上且沿所述电动机的轴向延伸的外凸缘; 并且所述总线环保持器沿所述电动机的径向布置在所述外凸缘的外侧，并且与所述外凸缘邻接。

    Semiconductor device having conducting structure
    4.
    发明授权
    Semiconductor device having conducting structure 失效
    具有导电结构的半导体器件

    公开(公告)号：US5793097A

    公开(公告)日：1998-08-11

    申请号：US519096

    申请日：1995-08-24

    申请人： Hiromi Shimamoto ,  Takashi Uchino ,  Takeo Shiba ,  Kazuhiro Ohnishi ,  Yoichi Tamaki ,  Takashi Kobayashi ,  Toshiyuki Kikuchi ,  Takahide Ikeda

    发明人： Hiromi Shimamoto ,  Takashi Uchino ,  Takeo Shiba ,  Kazuhiro Ohnishi ,  Yoichi Tamaki ,  Takashi Kobayashi ,  Toshiyuki Kikuchi ,  Takahide Ikeda

    IPC分类号： H01C7/06 ,  H01L21/02 ,  H01L21/822 ,  H01L27/04 ,  H01L27/06 ,  H01L29/00 ,  H01L23/48 ,  H01L29/76

    CPC分类号： H01L27/0652 ,  H01L27/0688 ,  H01L28/20

    摘要： The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.

    摘要翻译： 本发明提供了一种其电阻值被控制的多晶硅导电结构（例如电阻器），并且可以相对于任何电阻值而言可以变化较小并且对温度的依赖性较小，及其制造方法。 使用至少包括具有大晶粒尺寸的第一多晶硅层和小晶粒尺寸的第二多晶硅层的两层结构，并且第一多晶硅层具有正的温度对电阻的依赖性，而第二多晶硅层的第二 多晶层具有负电阻的温度依赖性，反之亦然。 此外，可以通过高剂量离子注入和退火，或者通过在不同温度下的化学气相沉积来沉积这些层，形成大晶粒和小晶粒层，可以形成大晶粒尺寸的多晶硅层。

    Method of manufacturing a BIMIS
    5.
    发明授权
    Method of manufacturing a BIMIS 失效
    制造BIMIS的方法

    公开(公告)号：US5773340A

    公开(公告)日：1998-06-30

    申请号：US563335

    申请日：1995-11-28

    申请人： Takahiro Kumauchi ,  Takashi Hashimoto ,  Osamu Kasahara ,  Satoshi Yamamoto ,  Yoichi Tamaki ,  Takeo Shiba ,  Takashi Uchino

    发明人： Takahiro Kumauchi ,  Takashi Hashimoto ,  Osamu Kasahara ,  Satoshi Yamamoto ,  Yoichi Tamaki ,  Takeo Shiba ,  Takashi Uchino

    IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/165 ,  H01L29/732 ,  H01L29/737

    CPC分类号： H01L21/8249 ,  Y10S148/152

    摘要： A method of manufacturing an improved bipolar transistor or BiCMOS having a phosphorus-doped polysilicon emitter electrode is disclosed. The method comprises forming an emitter electrode wherein a phosphorus-doped amorphous silicon film is deposited at temperature not higher than 540.degree. C. and then subjected to low temperature annealing treatment at a temperature of 600.degree. C. to 750.degree. C., under which the amorphous silicon is converted to a polysilicon and the phosphorus present in the amorphous silicon film is diffused into a base region to form an emitter region, followed by high temperature/short time annealing treatment at a temperature of 900.degree. C. to 950.degree. C. so that an activation rate of an impurity in a boron-doped polysilicon base electrode or source-drain regions of MOS.cndot.FET is improved.

    摘要翻译： 公开了一种制造具有磷掺杂多晶硅发射极电极的改进的双极晶体管或BiCMOS的方法。 该方法包括形成发射电极，其中磷掺杂的非晶硅膜在不高于540℃的温度下沉积，然后在600℃至750℃的温度下进行低温退火处理， 将非晶硅转化为多晶硅，将存在于非晶硅膜中的磷扩散到基极区域，形成发射极区域，然后在900℃〜950℃的温度下进行高温/短时退火处理 从而提高了掺杂多晶硅的多晶硅基极或MOSFET的源极 - 漏极区域中的杂质的活化速率。

    Non-volatile multi-state memory device with memory cell capable of storing multi-state data
    6.
    发明授权
    Non-volatile multi-state memory device with memory cell capable of storing multi-state data 失效
    具有能够存储多状态数据的存储单元的非易失性多状态存储器件

    公开(公告)号：US5761117A

    公开(公告)日：1998-06-02

    申请号：US697687

    申请日：1996-08-29

    申请人： Takashi Uchino ,  Nozomu Nambu ,  Akio Hagiwara

    发明人： Takashi Uchino ,  Nozomu Nambu ,  Akio Hagiwara

    IPC分类号： G11C17/00 ,  G11C11/56 ,  G11C16/02 ,  G11C11/34

    CPC分类号： G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C2211/5642 ,  G11C7/16

    摘要： Inputted digital data are held in a data register and converted to multi-state analog amount by a resistance dividing circuit and a decoder. A comparator compares an analog amount read from a non-volatile memory cell with a converted analog amount; and in accordance with this comparison result, a writing voltage is supplied to a memory cell. A first bias generating circuit is provided for generating two different types of bias voltages as this writing voltage, MOS transistors are inserted as respective switches to the bias voltage supply lines and writing voltages are switched by selectively ON/OFF-controlling one of the MOS transistors in accordance with the upper bit of the inputted digital data. As a result, unnecessary writing time can be eliminated, time required for executing writing can be reduced and circuit configuration can be simplified.

    摘要翻译： 输入的数字数据保存在数据寄存器中，并通过电阻分割电路和解码器转换成多状态模拟量。 比较器将从非易失性存储单元读取的模拟量与转换的模拟量进行比较; 并且根据该比较结果，向存储单元提供写入电压。 提供第一偏置产生电路，用于产生两种不同类型的偏置电压作为该写入电压，将MOS晶体管作为各自的开关插入到偏压电源线，并且通过选择性地对/ 根据输入的数字数据的高位。 结果，可以消除不必要的写入时间，可以减少执行写入所需的时间，并且可以简化电路配置。

    Inverter type AC generator with a zero-crossing detection circuit used to provide a synchronized operation and method of operating the same
    8.
    发明授权
    Inverter type AC generator with a zero-crossing detection circuit used to provide a synchronized operation and method of operating the same 失效
    具有过零检测电路的变频器型交流发电机，用于提供同步运行及其运行方法

    公开(公告)号：US07652900B2

    公开(公告)日：2010-01-26

    申请号：US11350299

    申请日：2006-02-07

    申请人： Mitsuo Fukaya ,  Takashi Uchino

    发明人： Mitsuo Fukaya ,  Takashi Uchino

    IPC分类号： H02M7/5387

    CPC分类号： H02J3/40 ,  H02M7/493

    摘要： An inverter type AC generator includes an inverter circuit converting a DC output into AC output of a predetermined frequency and supplying the AC output to a load via a load line in order to improve the quality of an AC output waveform at least in parallel operations. The inverter AC generator includes a zero-crossing detection circuit for detecting a timing of zero-crossings of an AC output voltage waveform on the output line. A controller generates a drive signal in synchronization with the timing of the detected zero-crossings, when a predetermined number of zero-crossings have been detected, and drives the inverter to perform a synchronized operation process.

    摘要翻译： 逆变器型交流发电机包括将DC输出转换成预定频率的AC输出的逆变器电路，并且通过负载线将AC输出提供给负载，以至少在并行操作中提高AC输出波形的质量。 逆变器交流发电机包括用于检测输出线路上的交流输出电压波形的过零的定时的过零检测电路。 当检测到预定数量的过零点时，控制器与检测到的过零点的定时同步地产生驱动信号，并驱动逆变器执行同步操作处理。

    Semiconductor device and process of producing the same
    10.
    发明申请
    Semiconductor device and process of producing the same 失效
    半导体器件及其制造方法

    公开(公告)号：US20050101097A1

    公开(公告)日：2005-05-12

    申请号：US11000092

    申请日：2004-12-01

    申请人： Hiromi Shimamoto ,  Takashi Uchino ,  Takeo Shiba ,  Kazuhiro Ohnishi ,  Yoichi Tamaki ,  Takashi Kobayashi ,  Toshiyuki Kikuchi ,  Takahide Ikeda

    发明人： Hiromi Shimamoto ,  Takashi Uchino ,  Takeo Shiba ,  Kazuhiro Ohnishi ,  Yoichi Tamaki ,  Takashi Kobayashi ,  Toshiyuki Kikuchi ,  Takahide Ikeda

    IPC分类号： H01C7/06 ,  H01L21/02 ,  H01L21/822 ,  H01L27/04 ,  H01L27/06 ,  H01L21/20 ,  H01L21/8222

    CPC分类号： H01L27/0652 ,  H01L27/0688 ,  H01L28/20

    摘要： The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline silicon layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.

    摘要翻译： 本发明提供了一种其电阻值被控制的多晶硅导电结构（例如电阻器），并且可以相对于任何电阻值而言可以变化较小并且对温度的依赖性较小，及其制造方法。 使用至少包括具有大晶粒尺寸的第一多晶硅层和小晶粒尺寸的第二多晶硅层的两层结构，并且第一多晶硅层具有正的温度对电阻的依赖性，而第二多晶硅层的第二 多晶硅层具有负电阻的温度依赖性，反之亦然。 此外，可以通过高剂量离子注入和退火，或者通过在不同温度下的化学气相沉积来沉积这些层，形成大晶粒和小晶粒层，可以形成大晶粒尺寸的多晶硅层。