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公开(公告)号：US06281665B1
公开(公告)日：2001-08-28
申请号：US09494298
申请日：2000-01-31
申请人： Takeshi Miyaba , Tooru Tanzawa , Masao Kuriyama
发明人： Takeshi Miyaba , Tooru Tanzawa , Masao Kuriyama
IPC分类号： G03F163
CPC分类号： G11C5/147
摘要： A first and a second transistor are connected to an output node. A first and a second differential amplifier compare a reference voltage with the voltage supplied from a voltage setting circuit. When the voltage at the output node is raised, the differential amplifier drives the first transistor, thereby charging the output node. In addition, when the voltage at the output node is lowered, the second differential amplifier drives the second transistor, thereby discharging the charges at the output node. The voltage setting circuit connected to the output node is composed of a current-summing D/A converter. In the voltage setting circuit, the value of the load resistance is varied according to the voltage appearing at the output node.
摘要翻译： 第一和第二晶体管连接到输出节点。 第一和第二差分放大器将参考电压与从电压设置电路提供的电压进行比较。 当输出节点的电压升高时，差分放大器驱动第一晶体管，从而对输出节点充电。 此外，当输出节点处的电压降低时，第二差分放大器驱动第二晶体管，从而在输出节点处放电。 连接到输出节点的电压设置电路由电流求和D / A转换器组成。 在电压设定电路中，负载电阻值根据输出节点出现的电压而变化。
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2.发明授权Intermediate voltage generating circuit and nonvolatile semiconductor memory having the same 失效中间电压发生电路和具有该中间电压产生电路的非易失性半导体存储器
公开(公告)号：US5877985A
公开(公告)日：1999-03-02
申请号：US881061
申请日：1997-06-24
申请人： Hironori Banba , Takeshi Miyaba
发明人： Hironori Banba , Takeshi Miyaba
CPC分类号： G11C5/147
摘要： A pull-up P-channel MOS transistor is connected between an output node and a VPP power supply terminal, while a pull-down N-channel MOS transistor is connected between the output node and a VSS power supply terminal. The output node has been electrically charged to VPP in an initial state. When a control signal SAEN has been made to be the "L" level, the change in the output node is gradually discharged. Since the output from the differential amplifying circuit is at the "H" level, the voltage at the output node is rapidly lowered. When the voltage at the output node has been made to be lower than a predetermined level, output voltage VOUT having a predetermined level is output.
摘要翻译： 上拉P沟道MOS晶体管连接在输出节点和VPP电源端子之间，而下拉N沟道MOS晶体管连接在输出节点和VSS电源端子之间。 在初始状态下，输出节点已经向VPP充电。 当控制信号SAEN为“L”电平时，输出节点的变化逐渐放电。 由于差分放大电路的输出为“H”电平，所以输出节点处的电压迅速降低。 当输出节点的电压低于预定电平时，输出具有预定电平的输出电压VOUT。
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公开(公告)号：US20060055452A1
公开(公告)日：2006-03-16
申请号：US11269696
申请日：2005-11-09
申请人： Toru Tanzawa , Takeshi Miyaba , Shigeru Atsumi
发明人： Toru Tanzawa , Takeshi Miyaba , Shigeru Atsumi
IPC分类号： G05F1/10
摘要： There are provided a boosted voltage generating circuit and a semiconductor memory device having the boosted voltage generating circuit which includes a booster circuit for outputting high voltage obtained by boosting the power supply voltage, a regulator circuit supplied with the high voltage, for generating voltage whose voltage value is smaller than the value of the high voltage and which is variably set to at least two values based on the high voltage at the operating time, and a equalizer circuit connected to the booster circuit and regulator circuit, for short-circuiting an output node of the booster circuit and an output node of the regulator circuit in response to a first control signal, wherein the operative period of the regulator circuit and the short-circuiting operation period of the equalizer circuit do not overlap each other.
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4.发明授权公开(公告)号：US06813130B2
公开(公告)日：2004-11-02
申请号：US10162610
申请日：2002-06-06
申请人： Takeshi Miyaba
发明人： Takeshi Miyaba
IPC分类号： H02H300
CPC分类号： H01L27/0251
摘要： A first power wire supplies a power potential to a circuit having a first function. A first ground wire supplies a ground potential to the circuit having the first function. A first protection circuit is connected between the first power wire and first ground wire, and protects the circuit having the first function. A second power wire supplies a power potential to a circuit having a second function. A second ground wire supplies a ground potential to the circuit having the second function. A second protection circuit is connected between the second power wire and the second ground wire, and protects the circuit having the second function. The element is disposed in at least one of intervals between the first power wire and the second power wire and between the first ground wire and the second ground wire, and brings one of the intervals into a disconnected state.
摘要翻译： 第一电源线向具有第一功能的电路提供电力电位。 第一接地线为具有第一功能的电路提供接地电位。 第一保护电路连接在第一电源线和第一接地线之间，并且保护具有第一功能的电路。 第二电源线将功率电势提供给具有第二功能的电路。 第二接地线为具有第二功能的电路提供接地电位。 第二保护电路连接在第二电源线和第二接地线之间，并且保护具有第二功能的电路。 元件设置在第一电源线和第二电力线之间以及第一接地线和第二接地线之间的至少一个间隔中，并且使间隔中的一个间隔成为断开状态。
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公开(公告)号：US06487120B2
公开(公告)日：2002-11-26
申请号：US09864181
申请日：2001-05-25
申请人： Toru Tanzawa , Takeshi Miyaba , Shigeru Atsumi
发明人： Toru Tanzawa , Takeshi Miyaba , Shigeru Atsumi
IPC分类号： G11C1604
摘要： There are provided a boosted voltage generating circuit and a semiconductor memory device having the boosted voltage generating circuit which includes a booster circuit for outputting high voltage obtained by boosting the power supply voltage, a regulator circuit supplied with the high voltage, for generating voltage whose voltage value is smaller than the value of the high voltage and which is variably set to at least two values based on the high voltage at the operating time, and a equalizer circuit connected to the booster circuit and regulator circuit, for short-circuiting an output node of the booster circuit and an output node of the regulator circuit in response to a first control signal, wherein the operative period of the regulator circuit and the short-circuiting operation period of the equalizer circuit do not overlap each other.
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公开(公告)号：US08213882B2
公开(公告)日：2012-07-03
申请号：US12724994
申请日：2010-03-16
申请人： Takashi Ueno , Takeshi Ueno , Takeshi Miyaba
发明人： Takashi Ueno , Takeshi Ueno , Takeshi Miyaba
CPC分类号： H04L25/0272 , H03F3/245 , H04L25/028
摘要： A common resistor is connected to load impedances that convert differential currents respectively generated by current sources into differential voltages. A constant current generated by the current sources is supplied to the common resistor to cause the common resistor to generate an in-phase current and set a common potential.
摘要翻译： 公共电阻连接到将电流源分别产生的差分电流转换为差分电压的负载阻抗。 由电流源产生的恒定电流被提供给公共电阻器，以使公共电阻器产生同相电流并设置公共电位。
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公开(公告)号：US07808280B2
公开(公告)日：2010-10-05
申请号：US12472744
申请日：2009-05-27
申请人： Takeshi Miyaba
发明人： Takeshi Miyaba
IPC分类号： H01L25/00
CPC分类号： H01L27/0207 , H01L27/11807 , H03K2217/0018
摘要： A semiconductor device includes multiple functional blocks, each having a predetermined function, and wiring regions on a substrate where a signal line is provided. The semiconductor device also includes multiple standard cells disposed in the wiring regions along the signal line, each of which operates with a substrate bias potential, and multiple contact cells disposed in the wiring region in parallel with the wiring direction of the signal line, each being associated with each of the multiple standard cells and providing the substrate bias potential to the associated standard cell.
摘要翻译： 半导体器件包括具有预定功能的多个功能块以及设置有信号线的基板上的布线区域。 半导体器件还包括沿着信号线的布线区域中设置的多个标准单元，每个布线区域都具有衬底偏置电位，并且布置在布线区域中的多个接触单元与信号线的布线方向平行 与多个标准单元中的每一个相关联并且向相关联的标准单元提供衬底偏置电位。
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公开(公告)号：US20090230995A1
公开(公告)日：2009-09-17
申请号：US12472744
申请日：2009-05-27
申请人： Takeshi MIYABA
发明人： Takeshi MIYABA
CPC分类号： H01L27/0207 , H01L27/11807 , H03K2217/0018
摘要： A semiconductor device includes multiple functional blocks, each having a predetermined function, and wiring regions on a substrate where a signal line is provided. The semiconductor device also includes multiple standard cells disposed in the wiring regions along the signal line, each of which operates with a substrate bias potential, and multiple contact cells disposed in the wiring region in parallel with the wiring direction of the signal line, each being associated with each of the multiple standard cells and providing the substrate bias potential to the associated standard cell.
摘要翻译： 半导体器件包括具有预定功能的多个功能块以及设置有信号线的基板上的布线区域。 半导体器件还包括沿着信号线的布线区域中设置的多个标准单元，每个布线区域都具有衬底偏置电位，并且布置在布线区域中的多个接触单元与信号线的布线方向平行 与多个标准单元中的每一个相关联并且向相关联的标准单元提供衬底偏置电位。
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9.发明授权Boosted voltage generating circuit and semiconductor memory device having the same 失效升压电压发生电路和具有该电压产生电路的半导体存储器件公开(公告)号：US07180796B2
公开(公告)日：2007-02-20
申请号：US11269697
申请日：2005-11-09
申请人： Toru Tanzawa , Takeshi Miyaba , Shigeru Atsumi
发明人： Toru Tanzawa , Takeshi Miyaba , Shigeru Atsumi
IPC分类号： G11C5/14
摘要： There are provided a boosted voltage generating circuit and a semiconductor memory device having the boosted voltage generating circuit which includes a booster circuit for outputting high voltage obtained by boosting the power supply voltage, a regulator circuit supplied with the high voltage, for generating voltage whose voltage value is smaller than the value of the high voltage and which is variably set to at least two values based on the high voltage at the operating time, and a equalizer circuit connected to the booster circuit and regulator circuit, for short-circuiting an output node of the booster circuit and an output node of the regulator circuit in response to a first control signal, wherein the operative period of the regulator circuit and the short-circuiting operation period of the equalizer circuit do not overlap each other.
摘要翻译： 提供了一种升压电压发生电路和具有升压电压产生电路的半导体存储器件，该升压电压产生电路包括用于输出通过升高电源电压而获得的高电压的升压电路，提供高电压的调节器电路，用于产生电压 值小于高电压值，并且基于工作时间的高电压可变地设置为至少两个值，以及连接到升压电路和调节器电路的均衡器电路，用于使输出节点短路 和所述调节器电路的输出节点响应于第一控制信号，其中所述调节器电路的操作周期和所述均衡器电路的短路操作周期彼此不重叠。
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公开(公告)号：US06996024B2
公开(公告)日：2006-02-07
申请号：US10866131
申请日：2004-06-14
申请人： Toru Tanzawa , Takeshi Miyaba , Shigeru Atsumi
发明人： Toru Tanzawa , Takeshi Miyaba , Shigeru Atsumi
IPC分类号： G11C11/00
摘要： There are provided a boosted voltage generating circuit and a semiconductor memory device having the boosted voltage generating circuit which includes a booster circuit for outputting high voltage obtained by boosting the power supply voltage, a regulator circuit supplied with the high voltage, for generating voltage whose voltage value is smaller than the value of the high voltage and which is variably set to at least two values based on the high voltage at the operating time, and a equalizer circuit connected to the booster circuit and regulator circuit, for short-circuiting an output node of the booster circuit and an output node of the regulator circuit in response to a first control signal, wherein the operative period of the regulator circuit and the short-circuiting operation period of the equalizer circuit do not overlap each other.
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