公开(公告)号：US08731050B2

公开(公告)日：2014-05-20

申请号：US12808887

申请日：2008-12-18

申请人： Takuma Chiba

发明人： Takuma Chiba

IPC分类号： H04N7/50

CPC分类号： H03M7/4006 ,  H03M7/40 ,  H04N19/196 ,  H04N19/46 ,  H04N19/61 ,  H04N19/70 ,  H04N19/91

摘要： An image encoding apparatus encodes image data and includes an image encoding unit that receives an input of the image data and image parameters and generates encoded image data by performing image encoding on the image data with reference to the image parameters and furthermore binarizing and arithmetically encoding the image data. A parameter processing unit outputs, as parameter information, parameters that are included in the image parameters and that are referred to when the encoded image data is arithmetically decoded, and encodes the image parameters to generate and output encoded image parameters. A stream generation unit generates a stream including the encoded image data obtained from the image encoding unit and the parameter information and the encoded image parameters that are outputted from the parameter processing unit.

摘要翻译： 图像编码装置对图像数据进行编码，并且包括图像编码单元，其接收图像数据和图像参数的输入，并且通过参照图像参数对图像数据执行图像编码来生成编码图像数据，并且进一步二进制化和算术编码 图像数据。 参数处理单元作为参数信息输出图像参数中包括的参数，并且在编码图像数据被算术解码时参考的参数，并对图像参数进行编码以生成和输出编码图像参数。 流生成单元生成包括从图像编码单元获得的编码图像数据和从参数处理单元输出的参数信息和编码图像参数的流。

公开(公告)号：US08059717B2

公开(公告)日：2011-11-15

申请号：US11585171

申请日：2006-10-24

申请人： Katsuo Saigo ,  Takuma Chiba

发明人： Katsuo Saigo ,  Takuma Chiba

IPC分类号： H04N7/12

CPC分类号： H04N19/42 ,  H04N19/11 ,  H04N19/136 ,  H04N19/176 ,  H04N19/593 ,  H04N19/61

摘要： An image coding apparatus that makes possible the parallelization of intra prediction, and outputs coded data that can be decoded by an image decoding apparatus compliant with the H.264 standard. The image coding apparatus performs orthogonal transformation, quantization, inverse quantization, inverse orthogonal transformation, and intra prediction on all blocks obtained when a single macroblock is divided into plural blocks, and includes: a predicted block control unit that causes all of the blocks to be intra predicted using at least one of the intra prediction modes specified in the H.264 standard on at least some of the blocks, in an order different from the raster scan order specified in the H.264 standard; and an sorting buffer that outputs, in the raster scan order, all the blocks intra predicted under the control of the predicted block control unit.

摘要翻译： 一种图像编码装置，其能够进行帧内预测的并行化，并且输出可以由符合H.264标准的图像解码装置解码的编码数据。 图像编码装置对单个宏块分割成多个块时所获得的所有块进行正交变换，量化，逆量化，逆正交变换和帧内预测，​​包括：使所有块成为 使用与H.264标准中规定的光栅扫描顺序不同的顺序，使用在至少一些块上的H.264标准中规定的帧内预测模式中的至少一个帧内预测; 以及排序缓冲器，以光栅扫描顺序输出在预测块控制单元的控制下预测的所有块。

公开(公告)号：US07876980B2

公开(公告)日：2011-01-25

申请号：US11271128

申请日：2005-11-10

申请人： Takuma Chiba ,  Kazuo Okamoto ,  Yuji Nagaishi ,  Tatsuro Juri

发明人： Takuma Chiba ,  Kazuo Okamoto ,  Yuji Nagaishi ,  Tatsuro Juri

IPC分类号： G06K9/22 ,  H04N1/04 ,  G06K9/00

CPC分类号： H04N5/23212 ,  H04N5/3454 ,  H04N5/3456 ,  H04N5/347 ,  H04N5/374

摘要： The resolution, frame rate, or both can be improved when imaging moving subjects in an imaging apparatus using a CMOS image sensor. The imaging apparatus has an image sensor having a two-dimensional array of pixels. Each of the pixels includes an element operable to produce an electric charge by photoelectrically converting light from an imaged subject and a part operable to accumulate the produced charge and output an accumulated charge or a signal representing the accumulated charge. The imaging apparatus also has an area control unit operable to define a specified area of the image sensor containing a plurality of pixels and an area density control unit operable to specify a density of pixels read from the specified area defined by the area control unit.

摘要翻译： 当使用CMOS图像传感器对成像设备中的移动物体进行成像时，可以提高分辨率，帧速率或两者。 成像装置具有具有二维像素阵列的图像传感器。 每个像素包括可操作以通过对来自成像对象的光进行光电转换来产生电荷的元件和可操作以累积所产生的电荷并输出累积电荷或表示累积电荷的信号的部分。 成像装置还具有区域控制单元，其可操作以限定包含多个像素的图像传感器的指定区域，以及区域密度控制单元，用于指定从区域控制单元定义的指定区域读取的像素的浓度。

公开(公告)号：US07860160B2

公开(公告)日：2010-12-28

申请号：US11354082

申请日：2006-02-15

申请人： Hiroaki Shimazaki ,  Takashi Masuno ,  Takuma Chiba ,  Kei Tasaka ,  Kenjiro Tsuda ,  Tatsuro Juri ,  Katsuo Saigo

发明人： Hiroaki Shimazaki ,  Takashi Masuno ,  Takuma Chiba ,  Kei Tasaka ,  Kenjiro Tsuda ,  Tatsuro Juri ,  Katsuo Saigo

IPC分类号： H04N7/12 ,  H04N9/12 ,  G06K9/46

CPC分类号： H04N19/152 ,  H04N19/61 ,  H04N19/91

摘要： The present invention provides a video encoding device in which a capacity of a binary data storing unit is small, a size of the video encoding device is small, a video signal can be processed in real time, and reduction in quality of images generated from the eventually obtained data can be prevented. The video encoding device according to the present invention includes: a video encoding unit which encodes a video signal; a binarization unit which binarizes an encoded value obtained from the video encoding unit; and an entropy encoding unit which subjects entropy encoding to binary data obtained from the binarization unit. Here, the video encoding unit encodes the video signal based on a characteristic of the binarization performed by the binarization unit, so that an amount of binary data obtained from the binarization unit by binarizing the encoded value that is encoded based on the characteristic is less than an amount of binary data obtained by binarizing an encoded value that is encoded without being based on the characteristic.

摘要翻译： 本发明提供了一种视频编码装置，其中二进制数据存储单元的容量小，视频编码装置的尺寸小，可以实时处理视频信号，并且降低从 可以防止最终获得的数据。 根据本发明的视频编码装置包括：视频编码单元，其对视频信号进行编码; 二值化单元，其将从所述视频编码单元获得的编码值二值化; 以及熵编码单元，其对来自二值化单元的二进制数据进行熵编码。 这里，视频编码单元基于由二值化单元执行的二值化的特性对视频信号进行编码，从而通过二值化基于特性编码的编码值从二值化单元获得的二进制数据量小于 通过对编码的值进行二值化而获得的二进制数据量，而不是基于特征。

公开(公告)号：US20090232205A1

公开(公告)日：2009-09-17

申请号：US12397777

申请日：2009-03-04

申请人： Takuma Chiba

发明人： Takuma Chiba

IPC分类号： H04N7/26 ,  H04L27/06 ,  H04N7/32

CPC分类号： H03M7/4006 ,  H04N19/13 ,  H04N19/44 ,  H04N19/61

摘要： The decoding apparatus enabling high-speed arithmetic decoding in decoding data coded using CABAC is an arithmetic decoding apparatus which receives, as input, coded data obtained by converting multivalue information of syntax into binary data then performing Context-based Adaptive Binary Arithmetic Coding on the binary data, and which decodes the coded data into the original multivalue information. During the reconstruction of the current binary data, the arithmetic decoding apparatus, parallelly calculates, in the same cycle, “next-next identifier code” candidates and “context index” candidates corresponding to the “next-next identifier code” candidates, and, in the next cycle, parallelly calculates, in the same cycle, a “next identifier code”, context index candidates corresponding to the next identifier code, and “probability variable” candidates corresponding to the “context index” candidates, and, when the current binary data reconstruction result is known, selects the respective calculation results according to the reconstruction result.

摘要翻译： 在使用CABAC编码的解码数据中进行高速算术解码的解码装置是算术解码装置，其接收通过将语法的多值信息转换为二进制数据而获得的编码数据，然后对二进制执行基于上下文的自适应二进制算术编码 数据，并将编码数据解码为原始多值信息。 在重构当前二进制数据期间，算术解码装置在同一周期中并行计算与“下一个标识符码”候选对应的“下一个下一标识码”候选和“上下文索引”候选， 在下一个周期中，在相同的周期中并行地计算与下一个标识符码对应的“下一个标识码”，上下文索引候选以及与“上下文索引”候选对应的“概率变量”候选，并且当当前 已知二进制数据重建结果，根据重建结果选择相应的计算结果。

公开(公告)号：US07439880B2

公开(公告)日：2008-10-21

申请号：US11822971

申请日：2007-07-11

申请人： Yukinaga Seki ,  Takuma Chiba ,  Tatsuro Juri ,  Kenjiro Tsuda

发明人： Yukinaga Seki ,  Takuma Chiba ,  Tatsuro Juri ,  Kenjiro Tsuda

IPC分类号： H03M7/34

CPC分类号： H04N19/174 ,  H04N19/12 ,  H04N19/13 ,  H04N19/149 ,  H04N19/152 ,  H04N19/172 ,  H04N19/176 ,  H04N19/61

摘要： An image coding device is provided that includes an image coding unit which codes image data, a binarization unit which binarizes the coded data, an intermediate buffer, an accumulated amount measuring unit which measures an amount of data in the intermediate buffer, and an I_PCM judging unit which compares the measured amount of data with a threshold. A buffer input selection unit is also provided which causes the intermediate buffer to accumulate next binary data when the amount of the data does not exceed the threshold and causes the intermediate buffer to accumulate next I_PCM data when the amount of the data exceeds the threshold. In addition, the device includes an arithmetic coding unit that arithmetically codes the binary data accumulated in the intermediate buffer and an output selection unit outputs the arithmetically coded data or the I_PCM data.

摘要翻译： 提供一种图像编码装置，其包括对图像数据进行编码的图像编码单元，对编码数据进行二值化的二值化单元，中间缓冲器，测量中间缓冲器中的数据量的累积量测量单元，以及I_PCM判断 将测量的数据量与阈值进行比较的单元。 还提供缓冲器输入选择单元，当数据量不超过阈值时，使中间缓冲器累积下一个二进制数据，并且当数据量超过阈值时使中间缓冲器累积下一个I_PCM数据。 此外，该装置包括对累积在中间缓冲器中的二进制数据进行算术编码的算术编码单元，输出选择单元输出算术编码数据或I_PCM数据。

公开(公告)号：US20080187051A1

公开(公告)日：2008-08-07

申请号：US12024726

申请日：2008-02-01

申请人： Takuma CHIBA ,  Takeshi TANAKA

发明人： Takuma CHIBA ,  Takeshi TANAKA

IPC分类号： H04N7/26

CPC分类号： H04N19/13 ,  H04N19/423

摘要： An image coding apparatus (100) which reduces buffer capacity to a minimum and includes an image coding processing unit (110) which generates intermediate data by executing a part of a process in the coding on the image data; a packetizing unit (120) which generates an image stream by executing a process other than the part of the process in the coding on the intermediate data, such as for example arithmetic coding, and packetizes the generated image stream in synchronization with the image stream generation process.

摘要翻译： 一种将缓冲器容量降至最低的图像编码装置（100），包括通过对图像数据执行编码处理的一部分来生成中间数据的图像编码处理单元（110） 打包单元（120），其通过执行除中间数据上的编码中的处理部分以外的处理（例如算术编码）来生成图像流，并且与图像流生成同步地分组生成的图像流 处理。

公开(公告)号：US06915406B2

公开(公告)日：2005-07-05

申请号：US10330322

申请日：2002-12-30

申请人： Takuma Chiba ,  Tsuyoshi Motokurumada ,  Iwao Yamazaki

发明人： Takuma Chiba ,  Tsuyoshi Motokurumada ,  Iwao Yamazaki

IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F12/00

CPC分类号： G06F12/1027 ,  G06F2212/681

摘要： A first table stores operand data for translation of operand virtual address into a physical address. A second table stores instruction data for translation of instruction virtual address into a physical address. The first and the second tables are formed in one memory. If operand access and instruction access are generated simultaneously, the operand access is executed with priority and the instruction virtual address is held in a wait register after that the instruction access is executed after finishing the operand access based on a wait instruction virtual address.

摘要翻译： 第一表存储用于将操作数虚拟地址转换为物理地址的操作数数据。 第二表存储用于将指令虚拟地址转换成物理地址的指令数据。 第一和第二表形成在一个存储器中。 如果同时产生操作数访问和指令访问，则优先执行操作数访问，并且在根据等待指令虚拟地址完成操作数访问之后执行指令访问之后，将指令虚拟地址保存在等待寄存器中。

公开(公告)号：US06895492B2

公开(公告)日：2005-05-17

申请号：US10330290

申请日：2002-12-30

申请人： Takuma Chiba

发明人： Takuma Chiba

IPC分类号： G06F12/10 ,  G06F12/00

CPC分类号： G06F12/1027 ,  G06F2212/681

摘要： A higher TLB that stores TLB data required for translating a virtual address into a physical address. A higher address translator performs address translation based on the TLB data according to an access. If address translation is not possible, the higher address translator requests a lower address translator to carry out the address translation. The lower address translator performs address translation based on a lower TLB. A shift register outputs a write prohibit signal to prohibit writing of the TLB data to the higher TLB, when write data that is the same as the write data has already been written in the higher TLB.

摘要翻译： 存储将虚拟地址转换为物理地址所需的TLB数据的较高TLB。 较高的地址转换器根据访问权限执行基于TLB数据的地址转换。 如果地址转换不可行，则较高地址转换器请求较低地址转换器进行地址转换。 较低地址转换器基于较低的TLB执行地址转换。 当写入数据与写入数据相同的写入数据已被写入较高的TLB时，移位寄存器输出写入禁止信号，以禁止将TLB数据写入较高的TLB。

公开(公告)号：US08675979B2

公开(公告)日：2014-03-18

申请号：US12937563

申请日：2009-12-11

申请人： Takuma Chiba ,  Kenjiro Tsuda ,  Tatsuro Juri ,  Yuki Kobayashi ,  Takashi Masuno ,  Katsuo Saigo ,  Yukinaga Seki ,  Hiroaki Shimazaki

发明人： Takuma Chiba ,  Kenjiro Tsuda ,  Tatsuro Juri ,  Yuki Kobayashi ,  Takashi Masuno ,  Katsuo Saigo ,  Yukinaga Seki ,  Hiroaki Shimazaki

IPC分类号： G06K9/46

CPC分类号： H04N19/40 ,  H04N19/107 ,  H04N19/11 ,  H04N19/157 ,  H04N19/176 ,  H04N19/61 ,  H04N19/86

摘要： A transcoder reduces the processing amount when a coded stream to which at least intra prediction is applied is transcoded into a coded stream to which intra prediction and inter prediction are applied. The transcoder converts a first coded stream to at least part of which intra prediction is applied, into a second coded stream to which intra prediction and inter prediction are applied. The transcoder includes a decoding unit that decodes the first coded stream to generate decoded image data; a prediction mode obtaining unit that obtains a prediction mode of intra prediction applied in decoding; and a coding unit that codes the decoded image data by applying the intra prediction or inter prediction to generate the second coded stream. A control unit controls causes the coding unit to use the prediction mode obtained by the prediction mode obtaining unit when the coding unit applies intra prediction.

摘要翻译： 当至少应用帧内预测的编码流被代码转换为应用帧内预测和帧间预测的编码流时，代码转换器减少处理量。 代码转换器将第一编码流转换为应用了帧内预测的至少一部分，被应用到帧内预测和帧间预测中的第二编码流中。 代码转换器包括解码单元，其对第一编码流进行解码以生成解码图像数据; 预测模式获取单元，其获得在解码中应用的帧内预测的预测模式; 以及编码单元，其通过应用帧内预测或帧间预测来生成第二编码流来对解码图像数据进行编码。 当编码单元应用帧内预测时，控制单元控制使得编码单元使用由预测模式获得单元获得的预测模式。