公开(公告)号：US5495115A

公开(公告)日：1996-02-27

申请号：US287276

申请日：1994-08-08

申请人： Makoto Kudo ,  Tomoyoshi Mishima ,  Takuma Tanimoto ,  Misuzu Sagawa

发明人： Makoto Kudo ,  Tomoyoshi Mishima ,  Takuma Tanimoto ,  Misuzu Sagawa

IPC分类号： H01L21/20 ,  H01L21/338 ,  H01L29/205 ,  H01L29/778 ,  H01L29/812 ,  H01S5/00 ,  H01S5/042

CPC分类号： H01L29/7783 ,  H01L29/205

摘要： A semiconductor crystalline laminate structure wherein between a first semiconductor layer consisting of a first alloyed semiconductor and a second semiconductor layer which has an energy gap wider than that of the first alloyed semiconductor and a lattice constant smaller than that of the first alloyed semiconductor and consists of one semiconductor selected from a group of single-element semiconductor, compound semiconductor, and alloyed semiconductor which contain no semiconductor having a largest lattice constant among the semiconductor constituting the first alloyed semiconductor, a third semiconductor layer which consists of a second alloyed semiconductor having an energy gap wider than that of the first alloyed semiconductor and contains the semiconductor having a largest lattice constant among the semiconductors constituting the first alloyed semiconductor is formed in contact with these layers, a forming method for the semiconductor crystalline laminate structure, and a semiconductor device using the method are indicated.

摘要翻译： 一种半导体结晶层叠结构，其中在由第一合金半导体构成的第一半导体层和具有比所述第一合金化半导体的能隙宽的能隙的第二半导体层之间，并且晶格常数小于所述第一合金化半导体的晶格常数，并且由 从构成第一合金化半导体的半导体中的不包含具有最大晶格常数的半导体的一组单元件半导体，化合物半导体和合金化半导体中选出的一个半导体，由具有能量的第二合金化半导体构成的第三半导体层 构成第一合金化半导体的半导体中具有最大晶格常数的半导体的间隙与这些层接触形成，半导体结晶层叠结构的形成方法和半导体结晶层叠结构 指示使用该方法的电感器件。

公开(公告)号：US5401357A

公开(公告)日：1995-03-28

申请号：US937781

申请日：1992-09-01

申请人： Hidekazu Okuhira ,  Tetsuo Ono ,  Susumu Hiraoka ,  Keizo Suzuki ,  Junji Shigeta ,  Hiroshi Masuda ,  Mitsuhiro Mori ,  Takuma Tanimoto ,  Shinichi Nakatsuka ,  Katsuhiko Mitani

发明人： Hidekazu Okuhira ,  Tetsuo Ono ,  Susumu Hiraoka ,  Keizo Suzuki ,  Junji Shigeta ,  Hiroshi Masuda ,  Mitsuhiro Mori ,  Takuma Tanimoto ,  Shinichi Nakatsuka ,  Katsuhiko Mitani

IPC分类号： H01L21/205 ,  H01L21/285 ,  H01L21/302 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/316 ,  H01L21/331 ,  H01L21/335 ,  H01L21/338 ,  H01L29/205 ,  H01L29/73 ,  H01L29/737 ,  H01L29/778 ,  H01L29/812 ,  B44C1/22

CPC分类号： H01L29/66318 ,  H01L21/28587 ,  H01L21/30621 ,  H01L21/3081 ,  H01L21/31654 ,  H01L29/66462

摘要： A method may be used to dry etch a sample including a plurality of regions different from each other in the photo-absorption of a light having a specified wavelength using an etching gas plasma. The method is capable of selectively etching the desired material from a plurality of materials having different types of band gap energies or from a plurality of materials having different band gap energies. The method includes a step of irradiating a light having the specified wavelength on the sample for reducing an etching rate of a region having a large photo-absorption coefficient to the light, thereby selectively etching a region having a small photo-absorption coefficient to the light.

摘要翻译： 在使用蚀刻气体等离子体对具有特定波长的光的光吸收中，可以使用一种方法来干蚀刻包括彼此不同的多个区域的样品。 该方法能够从具有不同类型的带隙能量的多种材料或具有不同带隙能量的多种材料中选择性地蚀刻所需的材料。 该方法包括在样品上照射具有特定波长的光以降低对光具有大的光吸收系数的区域的蚀刻速率的步骤，从而选择性地将具有小的光吸收系数的区域蚀刻到光 。

公开(公告)号：US5548138A

公开(公告)日：1996-08-20

申请号：US120818

申请日：1993-09-15

申请人： Takuma Tanimoto ,  Makoto Kudo ,  Tomoyoshi Mishima ,  Akishige Nakajima ,  Mitsuhiro Mori ,  Masao Yamane

发明人： Takuma Tanimoto ,  Makoto Kudo ,  Tomoyoshi Mishima ,  Akishige Nakajima ,  Mitsuhiro Mori ,  Masao Yamane

IPC分类号： H01L29/205 ,  H01L21/331 ,  H01L21/338 ,  H01L29/68 ,  H01L29/73 ,  H01L29/737 ,  H01L29/778 ,  H01L29/80 ,  H01L29/812 ,  H01L31/0328 ,  H01L31/0336

CPC分类号： H01L29/7376 ,  H01L29/802

摘要： In a semiconductor device using tunnel current and a barrier layer, arrangements are provided to lower the resistance of the semiconductor device. In particular, arrangements are provided to lower the parasitic resistance of a device such as a field effect transistor or an HBT, as well as to provide high-performance low noise amplifiers, mixers and the like using such reduced resistance semiconductor devices. To achieve this reduced resistance, carrier concentration or effective mass is designed not to be uniform in at least one of the semiconductor layers holding a barrier layer therebetween. For example, in an area near the barrier layer, the carrier concentration distribution can be large or the effective mass distribution can be small.

摘要翻译： 在使用隧道电流和阻挡层的半导体器件中，提供了降低半导体器件的电阻的布置。 特别地，提供了降低诸如场效应晶体管或HBT的器件的寄生电阻的布置，以及使用这种降低电阻的半导体器件来提供高性能低噪声放大器，混频器等。 为了实现这种降低的电阻，在其间保持阻挡层的至少一个半导体层中设计载流子浓度或有效质量不均匀。 例如，在阻挡层附近的区域中，载流子浓度分布可以较大，有效质量分布可以较小。