公开(公告)号：US5003366A

公开(公告)日：1991-03-26

申请号：US542796

申请日：1990-06-25

申请人： Tomoyoshi Mishima ,  Junichi Kasai ,  Yoshimasa Murayama

发明人： Tomoyoshi Mishima ,  Junichi Kasai ,  Yoshimasa Murayama

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L29/06 ,  H01L29/10 ,  H01L29/201 ,  H01L29/70 ,  H01L29/72 ,  H01L29/737

CPC分类号： H01L29/7376 ,  H01L29/1004 ,  Y10S977/759 ,  Y10S977/936

摘要： The present invention provides a hetero-junction bipolar transistor (HBT) whichis so designed that the emitter injection efficiency is improved, the base transit time and base resistance are reduced and yet the lowering of the collector injection efficiency is suppressed, by forming at least one quantum well in a base region of the HBT and determining the width of one of the quantum levels formed in the quantum well and the energy in a barrier layer constituting the quantum well is within kT/2.

公开(公告)号：US4914488A

公开(公告)日：1990-04-03

申请号：US189179

申请日：1988-05-02

申请人： Masao Yamane ,  Tomoyoshi Mishima ,  Shigeo Goto ,  Susumu Takahashi ,  Makoto Morioka

发明人： Masao Yamane ,  Tomoyoshi Mishima ,  Shigeo Goto ,  Susumu Takahashi ,  Makoto Morioka

IPC分类号： H01L21/22 ,  H01L21/335 ,  H01L29/15 ,  H01L29/778

CPC分类号： H01L29/66462 ,  H01L21/22 ,  H01L29/155 ,  H01L29/7783 ,  H01L29/7787

摘要： A compound semiconductor structure in the form of a superlattice film with effectively graded average composition, comprising an alternating lamination of two kinds of layers of different composition to form pairs of layers, the ratio of the thickness of one layer to the thickness of the other in said pairs of layers being gradually varied in the direction of thickness throughout successive pairs, thereby the average composition being effectively graded throughout the pairs. In a hetero-junction field effect transistor, the layer of effectively graded composition is used between a semiconductor layer making low resistance contact with a current-supplying electrode and a semiconductor layer where a two dimensional channel is to be formed. In case of AlGaAs/GaAs system, the Al composition is varied. When the superlattice film is heat-treated, Al in the AlGaAs layer diffuses into the GaAs layer, yielding a film with actually smoothly graded Al mole fraction.

摘要翻译： 具有有效分级平均组成的超晶格膜形式的化合物半导体结构，包括两种不同组成的层的交替叠层以形成一对层，一层的厚度与另一层的厚度之比 所述成对的层在整个连续的对中在厚度方向上逐渐变化，从而平均组成在整个对中有效地分级。 在异质结场效应晶体管中，在与供电电极进行低电阻接触的半导体层与要形成二维沟道的半导体层之间使用有效梯度组成的层。 在AlGaAs / GaAs系统的情况下，Al组成是变化的。 当超晶格膜被热处理时，AlGaAs层中的Al扩散到GaAs层中，产生具有平滑分级的Al摩尔分数的膜。

公开(公告)号：US20090001423A1

公开(公告)日：2009-01-01

申请号：US11902964

申请日：2007-09-26

申请人： Tomoyoshi Mishima ,  Toru Nakamura ,  Masataka Sato ,  Kazutaka Nomoto

发明人： Tomoyoshi Mishima ,  Toru Nakamura ,  Masataka Sato ,  Kazutaka Nomoto

IPC分类号： H01L29/778 ,  H01L21/338

CPC分类号： H01L29/7787 ,  H01L29/0843 ,  H01L29/2003 ,  H01L29/66462

摘要： A field-effect transistor is composed of a substrate, an electron transport layer and an electron supply layer formed sequentially on the substrate, wherein the electron transport layer and the electron supply layer are formed of a nitride semiconductor, a gate electrode, a source electrode and a drain electrode formed on the electron supply layer; and two high impurity concentration regions located in a depth direction directly below the source electrode and the drain electrode, respectively, the two high impurity concentration regions being formed to sandwich a two-dimensional electron gas layer formed between the electron transport layer and the electron supply layer. The two high impurity concentration regions each have a higher impurity concentration than the electron transport layer and the electron supply layer located directly below the gate electrode. The electron supply layer has a substantially flat surface between the source electrode and the gate electrode and between the drain electrode and the gate electrode.

摘要翻译： 场效应晶体管由基板，电子传输层和依次形成在基板上的电子供给层构成，其中电子传输层和电子供给层由氮化物半导体，栅电极，源电极 和形成在电子供给层上的漏电极; 以及分别位于源电极和漏电极正下方的深度方向的两个高杂质浓度区域，形成两个高杂质浓度区域以夹持形成在电子传输层和电子源之间的二维电子气层 层。 两个高杂质浓度区域各自具有比位于栅电极正下方的电子传输层和电子供给层更高的杂质浓度。 电子供给层在源电极和栅电极之间以及漏电极和栅电极之间具有基本平坦的表面。

公开(公告)号：US5548138A

公开(公告)日：1996-08-20

申请号：US120818

申请日：1993-09-15

申请人： Takuma Tanimoto ,  Makoto Kudo ,  Tomoyoshi Mishima ,  Akishige Nakajima ,  Mitsuhiro Mori ,  Masao Yamane

发明人： Takuma Tanimoto ,  Makoto Kudo ,  Tomoyoshi Mishima ,  Akishige Nakajima ,  Mitsuhiro Mori ,  Masao Yamane

IPC分类号： H01L29/205 ,  H01L21/331 ,  H01L21/338 ,  H01L29/68 ,  H01L29/73 ,  H01L29/737 ,  H01L29/778 ,  H01L29/80 ,  H01L29/812 ,  H01L31/0328 ,  H01L31/0336

CPC分类号： H01L29/7376 ,  H01L29/802

摘要： In a semiconductor device using tunnel current and a barrier layer, arrangements are provided to lower the resistance of the semiconductor device. In particular, arrangements are provided to lower the parasitic resistance of a device such as a field effect transistor or an HBT, as well as to provide high-performance low noise amplifiers, mixers and the like using such reduced resistance semiconductor devices. To achieve this reduced resistance, carrier concentration or effective mass is designed not to be uniform in at least one of the semiconductor layers holding a barrier layer therebetween. For example, in an area near the barrier layer, the carrier concentration distribution can be large or the effective mass distribution can be small.

摘要翻译： 在使用隧道电流和阻挡层的半导体器件中，提供了降低半导体器件的电阻的布置。 特别地，提供了降低诸如场效应晶体管或HBT的器件的寄生电阻的布置，以及使用这种降低电阻的半导体器件来提供高性能低噪声放大器，混频器等。 为了实现这种降低的电阻，在其间保持阻挡层的至少一个半导体层中设计载流子浓度或有效质量不均匀。 例如，在阻挡层附近的区域中，载流子浓度分布可以较大，有效质量分布可以较小。

公开(公告)号：US4672406A

公开(公告)日：1987-06-09

申请号：US684691

申请日：1984-12-21

申请人： Yasushi Sawada ,  Kiichi Ueyanagi ,  Yoshifumi Katayama ,  Yasuhiro Shiraki ,  Makoto Morioka ,  Takao Kuroda ,  Tomoyoshi Mishima

发明人： Yasushi Sawada ,  Kiichi Ueyanagi ,  Yoshifumi Katayama ,  Yasuhiro Shiraki ,  Makoto Morioka ,  Takao Kuroda ,  Tomoyoshi Mishima

IPC分类号： H01L29/812 ,  H01L21/338 ,  H01L21/8252 ,  H01L27/095 ,  H01L29/201 ,  H01L29/205 ,  H01L29/36 ,  H01L29/43 ,  H01L29/47 ,  H01L29/778 ,  H01L29/80

CPC分类号： H01L21/8252 ,  H01L27/095 ,  H01L29/432 ,  H01L29/475 ,  H01L29/7783

摘要： A semiconductor member has a structure wherein a first semiconductor layer is held between second and third semiconductor layers which have forbidden band widths greater than a forbidden band width of the first semiconductor layer, and wherein only the second semiconductor layer which is formed on a side of the first semiconductor layer close to a substrate is doped with impurities. The semiconductor member constructs the depletion type with the first and second semiconductor layers, and the enhancement type with the first and third semiconductor layers. A semiconductor device can be properly formed in the enhancement or depletion type by selectively connecting the semiconductor layers.

摘要翻译： 半导体部件具有这样的结构，其中第一半导体层被保持在禁止带宽大于第一半导体层的禁带宽度的第二和第三半导体层之间，并且其中只有形成在第一半导体层 靠近基板的第一半导体层掺杂有杂质。 半导体部件利用第一和第二半导体层构成耗尽型，并且利用第一和第三半导体层构成增强型。 可以通过选择性地连接半导体层，以增强或耗尽型形式适当地形成半导体器件。

公开(公告)号：US08835930B2

公开(公告)日：2014-09-16

申请号：US13426527

申请日：2012-03-21

申请人： Tadayoshi Tsuchiya ,  Naoki Kaneda ,  Tomoyoshi Mishima

发明人： Tadayoshi Tsuchiya ,  Naoki Kaneda ,  Tomoyoshi Mishima

IPC分类号： H01L29/15 ,  H01L31/0256 ,  H01L33/00 ,  H01L29/20 ,  H01L29/30 ,  H01L29/861 ,  H01L33/32

CPC分类号： H01L29/861 ,  H01L29/2003 ,  H01L33/0004 ,  H01L33/32

摘要： A gallium nitride rectifying device includes a p-type gallium nitride based semiconductor layer and an n-type gallium nitride based semiconductor layer, the two layers forming a pn junction with each other. The p-type gallium nitride based semiconductor layer has a carrier trap (level) density of not more than 1×1018 cm−3, or the n-type gallium nitride based semiconductor layer has a carrier trap (level) density of not more than 1×1016 cm−3.

摘要翻译： 氮化镓整流装置包括p型氮化镓基半导体层和n型氮化镓基半导体层，所述两层形成彼此的pn结。 p型氮化镓系半导体层具有1×10 18 cm -3以下的载流子阱（等级）密度，或n型氮化镓系半导体层的载流子阱（水平）密度不大于 1×1016cm-3。

公开(公告)号：US20090026499A1

公开(公告)日：2009-01-29

申请号：US12019137

申请日：2008-01-24

申请人： Takeshi Kikawa ,  Shinichiro Takatani ,  Tomihisa Yukimoto ,  Yohei Otoki ,  Hiroyuki Kamogawa ,  Tomoyoshi Mishima

发明人： Takeshi Kikawa ,  Shinichiro Takatani ,  Tomihisa Yukimoto ,  Yohei Otoki ,  Hiroyuki Kamogawa ,  Tomoyoshi Mishima

IPC分类号： H01L29/78

CPC分类号： H01L29/7783 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02389 ,  H01L21/02392 ,  H01L21/02395 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02461 ,  H01L21/02463 ,  H01L27/0605 ,  H01L29/155 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/8605

摘要： A semiconductor integrated circuit device having a plurality of semiconductor electronic members including a field effect transistor, intended for suppressing a sidegating effect on the field effect transistor, wherein accumulation of majority carriers of the field effect transistor is suppressed at the interface of heterojunction in the buffering compound semiconductor layer and the interface between the substrate and the buffering compound semiconductor layer in the device isolation region so that the discontinuity of energy forbidden bands of the semiconductors caused at the interfaces does not form a potential barrier upon conduction of the carriers into the substrate, whereby the sidegating effect from the resistor element, etc. placed adjacently to the field effect transistor can be decreased drastically.

摘要翻译： 一种半导体集成电路器件，具有多个包括场效应晶体管的半导体电子元件，旨在抑制场效应晶体管的侧向效应，其中场效应晶体管的多数载流子的积累被抑制在缓冲中的异质结界面处 化合物半导体层以及衬底和器件隔离区中的缓冲化合物半导体层之间的界面，使得在界面处引起的半导体的能量禁带的不连续性在载体传导到衬底中时不形成势垒， 从而可以显着降低来自与场效应晶体管相邻放置的电阻元件等的侧向起作用。

公开(公告)号：US06735353B2

公开(公告)日：2004-05-11

申请号：US10301641

申请日：2002-11-22

申请人： Koji Hirata ,  Masataka Shirai ,  Tomoyoshi Mishima

发明人： Koji Hirata ,  Masataka Shirai ,  Tomoyoshi Mishima

IPC分类号： G02B636

CPC分类号： G02B6/4201 ,  H01L2224/49171 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/00

摘要： The present invention provides a module for optical transmitter formed as an opto-electronic integrated circuit (OEIC) for reducing the heat generated at a driver circuit for modulator and stabilizing the thermal fluctuation in an optical modulator. For promoting the heat dissipation of the top face of the driver circuit for modulator of the OEIC chip, a protruding cooling plate is formed on metal wiring. A part of a semiconductor substrate present between the optical modulator and the driver circuit for modulator is thinned or removed. Further, a carrier for mounting thereon the OEIC chip is divided into two parts, and a peltier cooler is connected to the optical modulator side. This achieves the promotion of heat dissipation from the top face of the driver circuit for modulator, the thermal separation between the optical modulator and the driver circuit for modulator, and the temperature stabilization due to the peltier cooler. The temperature rise and the temperature change of the optical modulator are suppressed, so that it is possible to manufacture a module for optical transmitter showing no characteristic deterioration, in which an optical modulator and a driver circuit for modulator are formed as an OEIC chip.

摘要翻译： 本发明提供了一种用于光发射器的模块，其形成为用于减少用于调制器的驱动电路产生的热量并稳定光调制器中的热波动的光电集成电路（OEIC）。为了促进顶面的散热 用于OEIC芯片的调制器的驱动电路，在金属布线上形成突出的冷却板。 存在于调制器的光调制器和驱动电路之间的半导体衬底的一部分被薄化或去除。 此外，用于安装OEIC芯片的载体被分成两部分，并且珀耳替尔冷却器连接到光调制器侧。 这实现了从用于调制器的驱动器电路的顶面，调制器和调制器的驱动器电路之间的热分离以及由于珀尔帖冷却器引起的温度稳定的散热的升高。温度升高和温度变化 光调制器被抑制，从而可以制造出一种光发送器模块，其中没有特征劣化，其中光调制器和用于调制器的驱动电路形成为OEIC芯片。

公开(公告)号：US06728283B2

公开(公告)日：2004-04-27

申请号：US10287519

申请日：2002-11-05

申请人： Makoto Kudo ,  Kiyoshi Ouchi ,  Tomoyoshi Mishima

发明人： Makoto Kudo ,  Kiyoshi Ouchi ,  Tomoyoshi Mishima

IPC分类号： H01S500

CPC分类号： B82Y20/00 ,  G02B6/4245 ,  H01S5/0028 ,  H01S5/18305 ,  H01S5/18311 ,  H01S5/322 ,  H01S5/3235 ,  H01S5/32366 ,  H01S5/3422

摘要： A semiconductor laser which has an active layer of a lattice strain of less than 2% of a thickness mean on a GaAs substrate and can be used in a long wavelength band of 1.3 &mgr;m band or more and a photo module which uses the semiconductor laser are provided. The semiconductor laser device has a first semiconductor layer 5 and second semiconductor layers 4, the layer 5 and the layers 4 forming a type-II heterojunction structure, in which an energy of conduction band edge of said first conductor layer 5 is larger than the energy of conduction band of said second semiconductor layers 4. The device has third semiconductor layers 6 as barrier layers formed on both sides of said type-II heterojunction structure. In the device, the second semiconductor layers 4 are arranged on both sides of the first semiconductor layer 5 and the thickness of the first semiconductor layer 5 is set in such a degree of thickness that a wave function of an electron of a quantum well formed by making the second semiconductor layer well layers is coupled.

摘要翻译： 在GaAs衬底上具有小于厚度平均值的2％的晶格应变的有源层的半导体激光器可以用于1.3μm或更大的长波长带和使用半导体激光器的光模块 提供。 半导体激光器件具有第一半导体层5和第二半导体层4，层5和形成II型异质结结构的层4，其中所述第一导体层5的导带边缘的能量大于能量 所述第二半导体层4的导带。该器件具有形成在所述II型异质结结构两侧的阻挡层的第三半导体层6。 在该器件中，第二半导体层4被布置在第一半导体层5的两侧，并且第一半导体层5的厚度被设置为使得量子阱的电子的波函数由 使得第二半导体层阱层被耦合。

公开(公告)号：US5481120A

公开(公告)日：1996-01-02

申请号：US164801

申请日：1993-12-10

申请人： Kazuhiro Mochizuki ,  Tomoyoshi Mishima ,  Tohru Nakamura ,  Hiroshi Masuda ,  Tomonori Tanoue ,  Tooru Haga ,  Yoshihisa Fujisaki

发明人： Kazuhiro Mochizuki ,  Tomoyoshi Mishima ,  Tohru Nakamura ,  Hiroshi Masuda ,  Tomonori Tanoue ,  Tooru Haga ,  Yoshihisa Fujisaki

IPC分类号： H01L21/331 ,  H01L29/08 ,  H01L29/20 ,  H01L29/45 ,  H01L29/737 ,  H01L29/80 ,  H01S5/042 ,  H01S5/183 ,  H01S5/22 ,  H01S5/323 ,  H01L27/02

CPC分类号： H01S5/18347 ,  H01L29/0891 ,  H01L29/20 ,  H01L29/452 ,  H01L29/66318 ,  H01L29/7371 ,  H01S5/0424 ,  H01L29/802 ,  H01S2304/02 ,  H01S5/18341 ,  H01S5/18369 ,  H01S5/32316

摘要： Disclosed is a semiconductor device using a polycrystalline compound semiconductor with a low resistance as a low resistance layer, and its fabrication method. The above polycrystalline compound semiconductor layer is doped with C or Be as impurities in a large amount, and is extremely low in resistance. The polycrystalline compound semiconductor layer is formed by either of a molecular beam epitaxy method, an organometallic vapor phase epitaxy method and an organometallic molecular beam epitaxy method under the condition that a substrate temperature is 450.degree. C. or less and the ratio of partial pressure of a V-group element to a III-group element is 50 or more. In the case that the above polycrystaline compound semiconductor layer with a low resistance is used as an extrinsic base region of an heterojunction bipolar transistor, since the extrinsic base region can be formed on a dielectric film formed on a collector, it is possible to reduce the base-collector capacitance, and hence to enhance the operational speed of the heterojunction bipolar transistor.

摘要翻译： 公开了使用具有低电阻的多晶化合物半导体作为低电阻层的半导体器件及其制造方法。 上述多晶化合物半导体层以C或Be作为杂质被大量掺杂，并且电阻极低。 多晶化合物半导体层通过分子束外延法，有机金属气相外延法和有机金属分子束外延法中的任一种形成，在基板温度为450℃以下的条件下， 对于III族元素的V族元素为50以上。 在上述具有低电阻的多晶化合物半导体层用作异质结双极晶体管的外在基极区域的情况下，由于可以在形成在集电体上的电介质膜上形成非本征基区，因此可以减少 基极集电极电容，从而提高异质结双极晶体管的工作速度。