公开(公告)号：US11049942B2

公开(公告)日：2021-06-29

申请号：US16680792

申请日：2019-11-12

申请人： Te-Chang Tseng ,  Riichiro Shirota

发明人： Riichiro Shirota ,  Yung-Yueh Chiu ,  Te-Chang Tseng ,  Hiroshi Watanabe

IPC分类号： H01L29/16 ,  H01L29/36 ,  H01L29/165 ,  H01L29/78 ,  H01L29/10

摘要： A semiconductor device based on SiC-MOSFET realizes high voltage endurance, high current, low breakover voltage, low switching loss and low noise. The SiC-MOSFET is a combination of a Si-MOSFET with high channel mobility and a drift layer formed by SiC with high bulk mobility, so that the first conductive SiC wafer forming the drift layer joins the second conductive Si wafer, excavates out a trench gate in part of the SiC to make the MOSFET, and a second conductive barrier layer is arranged in the Si region adjacent to the SiC.

公开(公告)号：US20200168707A1

公开(公告)日：2020-05-28

申请号：US16680792

申请日：2019-11-12

申请人： TE-CHANG TSENG ,  RIICHIRO SHIROTA

发明人： RIICHIRO SHIROTA ,  YUNG-YUEH CHIU ,  TE-CHANG TSENG ,  HIROSHI WATANABE

IPC分类号： H01L29/16 ,  H01L29/36 ,  H01L29/10

摘要： A semiconductor device based on SiC-MOSFET realizes high voltage endurance, high current, low breakover voltage, low switching loss and low noise. The SiC-MOSFET is a combination of a Si-MOSFET with high channel mobility and a drift layer formed by SiC with high bulk mobility, so that the first conductive SiC wafer forming the drift layer joins the second conductive Si wafer, excavates out a trench gate in part of the SiC to make the MOSFET, and a second conductive barrier layer is arranged in the Si region adjacent to the SiC.

公开(公告)号：US08131954B2

公开(公告)日：2012-03-06

申请号：US12338420

申请日：2008-12-18

申请人： Chun-Yi Tu ,  Te-Chang Tseng ,  Hideki Arakawa ,  Takeshi Nakayama

发明人： Chun-Yi Tu ,  Te-Chang Tseng ,  Hideki Arakawa ,  Takeshi Nakayama

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G11C16/0483 ,  G11C16/10

摘要： A memory device is provided. The memory device includes a memory array formed by a plurality of multi level cells, a determining circuit and a data reading circuit. The memory array includes a plurality of page units, each including a main data and an auxiliary data corresponding to the main data, wherein the auxiliary data includes a plurality of flag bits. The determining circuit generates a determination bit according to the flag bits. The data reading circuit obtains information corresponding to the main data according to the determination bit.

摘要翻译： 提供存储器件。 存储器件包括由多个多电平单元形成的存储器阵列，确定电路和数据读取电路。 存储器阵列包括多个页面单元，每个页面单元包括主数据和与主数据相对应的辅助数据，其中辅助数据包括多个标志位。 确定电路根据标志位产生确定位。 数据读取电路根据确定位获取与主数据相对应的信息。

公开(公告)号：US07778087B2

公开(公告)日：2010-08-17

申请号：US12335784

申请日：2008-12-16

申请人： Chun-Yi Tu ,  Te-Chang Tseng ,  Hideki Arakawa ,  Takeshi Nakayama

发明人： Chun-Yi Tu ,  Te-Chang Tseng ,  Hideki Arakawa ,  Takeshi Nakayama

IPC分类号： G11C16/04

CPC分类号： G11C16/10

摘要： A memory programming method is provided. A first programming operation is performed to program a multi level cell from an initial state to a first target state, which corresponds to a storage data and has a first threshold voltage range. A flag bit of the NAND flash is set to a first state to indicate that the first programming operation has been performed. A second programming operation is performed to program the multi level cell from the first target state to a second target state, which corresponds to the storage data and has a second threshold voltage range. The flag bit is set to a second state to indicate that the second programming operation has been performed.

摘要翻译： 提供了存储器编程方法。 执行第一编程操作以将多级单元从初始状态编程到对应于存储数据的第一目标状态，并具有第一阈值电压范围。 NAND闪存的标志位被设置为第一状态以指示已经执行了第一编程操作。 执行第二编程操作以将多级单元从第一目标状态编程为对应于存储数据并具有第二阈值电压范围的第二目标状态。 标志位被设置为第二状态以指示已经执行了第二编程操作。

公开(公告)号：US08278952B2

公开(公告)日：2012-10-02

申请号：US12335062

申请日：2008-12-15

申请人： Te-Chang Tseng ,  Chun-Yi Tu ,  Yamasaki Kyoji

发明人： Te-Chang Tseng ,  Chun-Yi Tu ,  Yamasaki Kyoji

IPC分类号： G01R31/3187 ,  G01R31/26 ,  G01R31/14

CPC分类号： G01R31/31721 ,  G01R31/3172 ,  Y10T307/696

摘要： A voltage adjusting circuit is provided. The voltage adjusting circuit for adjusting the output voltages supplied by voltage sources includes a test control device, a multiplexer, a comparator, and a built in self test (BIST) device. The test control device selects one of the voltage sources as a testing voltage source, and outputs a selecting command for selecting the testing voltage source and a target voltage corresponding to the testing voltage source. The multiplexer is coupled to the voltage sources, receives an enablement signal, and outputs a voltage supplied by the testing voltage source as a testing voltage according to the enablement signal. The comparator compares the voltage levels of the testing voltage and the target voltage, and outputs a comparison result. The BIST device receives the selecting command, outputs the enablement signal for enabling the testing voltage source according to the selecting command, and adjusts the voltage supplied by the testing voltage source to a predetermined voltage according to the comparison result.

摘要翻译： 提供电压调节电路。 用于调节由电压源提供的输出电压的电压调节电路包括测试控制装置，多路复用器，比较器和内置自检（BIST）装置。 测试控制装置选择一个电压源作为测试电压源，并且输出用于选择测试电压源的选择指令和对应于测试电压源的目标电压。 多路复用器耦合到电压源，接收使能信号，并根据启用信号输出由测试电压源提供的电压作为测试电压。 比较器比较测试电压和目标电压的电压电平，并输出比较结果。 BIST设备接收选择命令，根据选择命令输出启用测试电压源的使能信号，并根据比较结果将测试电压源提供的电压调整到预定电压。

公开(公告)号：US08274827B2

公开(公告)日：2012-09-25

申请号：US12780938

申请日：2010-05-17

申请人： Riichiro Shirota ,  Te-Chang Tseng

发明人： Riichiro Shirota ,  Te-Chang Tseng

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C5/063 ,  G11C8/14

摘要： The invention provides a memory device on a substrate. The memory device comprises semiconductor layers, common word lines, common bit lines and a common source line. The semiconductor layers are stacked on the substrate, wherein each semiconductor layer has a plurality of NAND strings, and each NAND string includes memory cells and at least a string selection transistor. The common word lines are configured above the semiconductor layers, wherein each common word line is coupled to the memory cells arranged in a same row of the semiconductor layers. The common bit lines are configured on the common word lines, wherein each common bit line is coupled to a first ends of the NAND strings arranged in the same column of the semiconductor layers. The common source line is configured on the common word lines and coupled to a second ends of the NAND strings of the semiconductor layers.

摘要翻译： 本发明提供了一种在衬底上的存储器件。 存储器件包括半导体层，公共字线，公共位线和公共源极线。 半导体层堆叠在基板上，其中每个半导体层具有多个NAND串，并且每个NAND串包括存储单元和至少一个串选择晶体管。 公共字线被配置在半导体层之上，其中每个公共字线耦合到布置在同一行半导体层中的存储单元。 公共位线配置在公共字线上，其中每个公共位线耦合到布置在半导体层的同一列中的NAND串的第一端。 公共源极线配置在公共字线上并耦合到半导体层的NAND串的第二端。

公开(公告)号：US20110280075A1

公开(公告)日：2011-11-17

申请号：US12780938

申请日：2010-05-17

申请人： Riichiro Shirota ,  Te-Chang Tseng

发明人： Riichiro Shirota ,  Te-Chang Tseng

IPC分类号： G11C16/04 ,  G11C11/34

CPC分类号： G11C16/0483 ,  G11C5/063 ,  G11C8/14

摘要： The invention provides a memory device on a substrate. The memory device comprises semiconductor layers, common word lines, common bit lines and a common source line. The semiconductor layers are stacked on the substrate, wherein each semiconductor layer has a plurality of NAND strings, and each NAND string includes memory cells and at least a string selection transistor. The common word lines are configured above the semiconductor layers, wherein each common word line is coupled to the memory cells arranged in a same row of the semiconductor layers. The common bit lines are configured on the common word lines, wherein each common bit line is coupled to a first ends of the NAND strings arranged in the same column of the semiconductor layers. The common source line is configured on the common word lines and coupled to a second ends of the NAND strings of the semiconductor layers.

摘要翻译： 本发明提供了一种在衬底上的存储器件。 存储器件包括半导体层，公共字线，公共位线和公共源极线。 半导体层堆叠在基板上，其中每个半导体层具有多个NAND串，并且每个NAND串包括存储单元和至少一个串选择晶体管。 公共字线被配置在半导体层之上，其中每个公共字线耦合到布置在同一行半导体层中的存储单元。 公共位线配置在公共字线上，其中每个公共位线耦合到布置在半导体层的同一列中的NAND串的第一端。 公共源极线配置在公共字线上并耦合到半导体层的NAND串的第二端。

公开(公告)号：US07903470B2

公开(公告)日：2011-03-08

申请号：US12335189

申请日：2008-12-15

申请人： Te-Chang Tseng ,  Chun-Yi Tu ,  Hideki Arakawa ,  Yamasaki Kyoji

发明人： Te-Chang Tseng ,  Chun-Yi Tu ,  Hideki Arakawa ,  Yamasaki Kyoji

IPC分类号： G11C11/34 ,  G11C16/06

CPC分类号： G11C16/16

摘要： An integrated circuit is provided. The integrated circuit includes a memory device and a discharge circuit. The discharge circuit discharges the well voltage line and the first voltage line of the memory device after the end of the erasing period and includes a first and second switch circuit and a first and second control voltage supplier. The first switch circuit is coupled between the well voltage line, the first voltage line and a second supplier. The second switch circuit is coupled between the first switch circuit and a reference voltage. The first control voltage supplier is coupled to the first switch circuit and supplies a first control voltage to turn on the first switch circuit during a first discharge period. The second control voltage supplier is coupled to the second switch circuit, and supplies a second control voltage to turn on the second switch circuit during a second discharge period.

摘要翻译： 提供集成电路。 集成电路包括存储器件和放电电路。 放电电路在擦除周期结束后对存储器件的阱电压线和第一电压线放电，并且包括第一和第二开关电路以及第一和第二控制电压供应器。 第一开关电路耦合在阱电压线，第一电压线和第二供电器之间。 第二开关电路耦合在第一开关电路和参考电压之间。 第一控制电压供应器耦合到第一开关电路，并且在第一放电期间提供第一控制电压以接通第一开关电路。 第二控制电压供应器耦合到第二开关电路，并且在第二放电周期期间提供第二控制电压以接通第二开关电路。

公开(公告)号：US20090161440A1

公开(公告)日：2009-06-25

申请号：US12335189

申请日：2008-12-15

申请人： Te-Chang TSENG ,  Chun-Yi Tu ,  Hideki ARAKAWA ,  Yamasaki KYOJI

发明人： Te-Chang TSENG ,  Chun-Yi Tu ,  Hideki ARAKAWA ,  Yamasaki KYOJI

IPC分类号： G11C16/14

CPC分类号： G11C16/16

摘要： An integrated circuit is provided. The integrated circuit includes a memory device and a discharge circuit. The discharge circuit discharges the well voltage line and the first voltage line of the memory device after the end of the erasing period and includes a first and second switch circuit and a first and second control voltage supplier. The first switch circuit is coupled between the well voltage line, the first voltage line and a second supplier. The second switch circuit is coupled between the first switch circuit and a reference voltage. The first control voltage supplier is coupled to the first switch circuit and supplies a first control voltage to turn on the first switch circuit during a first discharge period. The second control voltage supplier is coupled to the second switch circuit, and supplies a second control voltage to turn on the second switch circuit during a second discharge period.

摘要翻译： 提供集成电路。 集成电路包括存储器件和放电电路。 放电电路在擦除周期结束后对存储器件的阱电压线和第一电压线进行放电，并且包括第一和第二开关电路以及第一和第二控制电压供应器。 第一开关电路耦合在阱电压线，第一电压线和第二供电器之间。 第二开关电路耦合在第一开关电路和参考电压之间。 第一控制电压供应器耦合到第一开关电路，并且在第一放电期间提供第一控制电压以接通第一开关电路。 第二控制电压供应器耦合到第二开关电路，并且在第二放电周期期间提供第二控制电压以接通第二开关电路。

公开(公告)号：US20090161426A1

公开(公告)日：2009-06-25

申请号：US12335784

申请日：2008-12-16

申请人： Chun-Yi TU ,  Te-Chang Tseng ,  Hideki Arakawa ,  Takeshi Nakayama

发明人： Chun-Yi TU ,  Te-Chang Tseng ,  Hideki Arakawa ,  Takeshi Nakayama

IPC分类号： G11C16/04

CPC分类号： G11C16/10

摘要： A memory programming method is provided. A first programming operation is performed to program a multi level cell from an initial state to a first target state, which corresponds to a storage data and has a first threshold voltage range. A flag bit of the NAND flash is set to a first state to indicate that the first programming operation has been performed. A second programming operation is performed to program the multi level cell from the first target state to a second target state, which corresponds to the storage data and has a second threshold voltage range. The flag bit is set to a second state to indicate that the second programming operation has been performed.

摘要翻译： 提供了存储器编程方法。 执行第一编程操作以将多级单元从初始状态编程到对应于存储数据的第一目标状态，并具有第一阈值电压范围。 NAND闪存的标志位被设置为第一状态以指示已经执行了第一编程操作。 执行第二编程操作以将多级单元从第一目标状态编程为对应于存储数据并具有第二阈值电压范围的第二目标状态。 标志位被设置为第二状态以指示已经执行了第二编程操作。