公开(公告)号：US5248972A

公开(公告)日：1993-09-28

申请号：US863063

申请日：1992-04-03

Applicant: Teppo Karema ,  Hannu Tenhunen ,  Tapani Ritoniemi

Inventor： Teppo Karema ,  Hannu Tenhunen ,  Tapani Ritoniemi

IPC: H03M3/02

CPC classification number: H03M3/366 ,  H03M3/43 ,  H03M3/448 ,  H03M3/452

Abstract: The invention relates to a method and an arrangement for stabilizing a high-order sigma-delta modulator comprising at least two integrator stages and a quantizing means. The first, the first two or the first three integrator stages of the high-order modulator form a low-order modulator which is stable at all input signal values. The arrangement comprises a means for resetting the integrator stages following the low-order modulator when the stable operation range of the high-order modulator is exceeded. For an MF modulator the arrangement further comprises a coupling means for decoupling the output of the last integrator of the high-order modulator from the quantizing means and for coupling the output of said low-order modulator to the quantizing means simultaneously with the resetting.

公开(公告)号：US5191331A

公开(公告)日：1993-03-02

申请号：US818522

申请日：1992-01-09

Applicant: Teppo Karema ,  Hannu Tenhunen ,  Tapani Ritoniemi

Inventor： Teppo Karema ,  Hannu Tenhunen ,  Tapani Ritoniemi

IPC: H03M3/02 ,  H03M7/00

CPC classification number: H03M7/3008 ,  H03M7/304

Abstract: The invention relates to a digital sigma-delta modulator for a D/A converter, comprising an integration stage or several cascaded integration stages and a feedback circuit for feedbacking the sign of the output signal of the last integration stage, delayed by one clock cycle and multiplied by a predetermined scaling coefficient, to each integration stage. To avoid limit cycle oscillation, the state of at least the least significant free bit in at least one integration stage is variable at random.

Abstract translation: 本发明涉及用于D / A转换器的数字Σ-Δ调制器，其包括积分级或多级联积分级和反馈电路，用于反馈最后一个积分级的输出信号的符号，延迟一个时钟周期， 乘以预定的缩放系数到每个积分级。 为了避免极限循环振荡，至少一个积分级中至少最低有效空闲位的状态是随机变化的。

公开(公告)号：US5629701A

公开(公告)日：1997-05-13

申请号：US256567

申请日：1994-08-11

Applicant: Tapani Ritoniemi ,  Teppo Karema ,  Hannu Tenhunen

Inventor： Tapani Ritoniemi ,  Teppo Karema ,  Hannu Tenhunen

IPC: H03M3/02 ,  H03M3/00

CPC classification number: H03M3/418

Abstract: The invention relates to a method for cascading two or more feedforward-type sigma-delta modulators, and a modulator system comprising at least two cascaded modulators (1, 2). According to the invention, each subsequent modulator (2) in the cascade quantizes the integrated signal estimate error (e) of the preceding modulator (1), the quantized error (e') is differentiated (3) and subtracted (6) from the quantized output signal (D") of the preceding modulator (1).

Abstract translation: PCT No.PCT / FI93 / 00027 Sec。 371日期：1994年8月11日 102（e）日期1994年8月11日PCT提交1993年1月28日PCT公布。 公开号WO93 / 15557 日期：1993年8月5日本发明涉及一种用于级联两个或多个前馈型Σ-Δ调制器的方法，以及包括至少两个级联调制器（1,2）的调制器系统。 根据本发明，级联中的每个后续调制器（2）量化前一个调制器（1）的积分信号估计误差（e），量化误差（e'）被差分（3）并从 量化的前一个调制器（1）的输出信号（D“）。