公开(公告)号：US5623497A

公开(公告)日：1997-04-22

申请号：US386660

申请日：1995-02-09

申请人： Kazuhiro Shimawaki ,  Tetsuo Sotome ,  Takayuki Nakajima

发明人： Kazuhiro Shimawaki ,  Tetsuo Sotome ,  Takayuki Nakajima

IPC分类号： G01R31/319 ,  G06F11/267 ,  H04L1/24 ,  G06F11/00

CPC分类号： G06F11/221 ,  H04L1/244

摘要： A bit error measurement apparatus is capable of easily specifying pattern conditions which cause bit errors in an incoming signal pattern without measuring all of a test pattern by measuring a bit error rate at a selected position or region of a test pattern. The bit error measurement apparatus includes a test pattern generator which generates the test pattern for verifying the incoming signal to be tested, a verifier which receives the incoming signal and the test pattern and generates a bit error detection signal when the incoming signal and the test pattern disagree, a pattern position detector which detects a measurement region of the test pattern when receiving a synchronizing signal from the test pattern generator and generates a count enable signal corresponding to the detected measurement region, and an error counter which counts the bit error detection signal from the verifier based on the count enable signal from the pattern position detector.

摘要翻译： 误差测量装置能够容易地指定在输入信号模式中引起位错误的模式条件，而不通过测量测试图案的选定位置或区域的误码率来测量所有测试图案。 比特误差测量装置包括产生用于验证待测试的输入信号的测试模式的测试模式发生器，接收输入信号和测试模式的验证器，并且当输入信号和测试模式 不同意，图案位置检测器，当从测试图案发生器接收到同步信号时检测测试图案的测量区域，并产生对应于检测到的测量区域的计数使能信号;以及错误计数器，其对来自 该验证器基于来自图案位置检测器的计数使能信号。

公开(公告)号：US5210754A

公开(公告)日：1993-05-11

申请号：US710522

申请日：1991-06-04

申请人： Toshiro Takahashi ,  Takayuki Nakajima ,  Tetsuo Sotome ,  Noboru Akiyama

发明人： Toshiro Takahashi ,  Takayuki Nakajima ,  Tetsuo Sotome ,  Noboru Akiyama

IPC分类号： H04L1/00 ,  H04J3/06 ,  H04L7/00

CPC分类号： H04J3/0608

摘要： An Nth one of N parallel sequences of low-speed data demultiplexed by a demultiplexer from high-speed input data in synchronization with a high-speed clock is compared by N comparators with N parallel sequences of reference patterns. The N parallel sequences of reference patterns are each generated in synchronization with a frequency divided clock obtained by frequency dividing the high-speed clock into 1/N. When any of the comparators provides a disagreement output at least once, one clock pulse is eliminated by a post-clock eliminating circuit from the divided clock so that the N sequences of reference patterns are each delayed by one bit. When a counter detects that any one of the comparators does not provide the disagreement signal for n consecutive bits, the sequence of reference patterns corresponding to this comparator and the Nth sequence of low-speed data are in synchronization with each other. Clock pulses of the number corresponding to the line position of the synchronized sequence of reference patterns are eliminated by a pre-clock eliminating circuit from the high-speed clock which is applied to the demultiplexer. By this, line positions of the N parallel sequences of low-speed data are sequentially shifted so that the Nth sequence of low-speed data assumes the same line position as that of the synchronized reference pattern, and as a result, the N parallel sequences of low-speed data are synchronized with the N parallel sequences of reference patterns, respectively.

公开(公告)号：US5150390A

公开(公告)日：1992-09-22

申请号：US748755

申请日：1991-08-20

申请人： Mishio Hayashi ,  Tetsuo Sotome

发明人： Mishio Hayashi ,  Tetsuo Sotome

IPC分类号： H03K3/78 ,  G01R31/319 ,  G06F1/025

CPC分类号： G01R31/31922 ,  G01R31/31919 ,  G01R31/31926 ,  G06F1/025

摘要： Frequency division circuits in n stages sequentially 1/2-frequency-divide an input clock signal. Pattern generating circuit generates and issues a plurality of pattern data parallel to each other in synchronism with a frequency-divided clock from the final frequency division stage thereof. Multiplexing circuits in n stages are given a plurality of pattern data and multiplex input pattern data in each stage for each two data. Output clock signals of the n-th through first stage frequency division circuits are supplied to the first through n-th multiplexing circuits via respective delay circuits as multiplexing control clock signals. A retiming circuit is inserted in series to the input of at least one of the multiplexing circuits, and a multiplexing control clock signal applied to said one multiplexing circuit from the corresponding frequency division circuit is given to the retiming circuit as a retiming clock signal. A phase switching circuit is inserted in series to the output of the frequency division circuit which applies the multiplexing control clock signal to said one multiplexing circuit. When a node of the input pattern data in the retiming circuit approaches the edge of a retiming clock signal within a predetermined range, an approach detection signal is issued from the approach detection circuit. The phase switching circuit shifts the phase of the input clock signal in response to the approach detection signal by a predetermined quantity and issues the phase-shifted clock signal.

公开(公告)号：US5761216A

公开(公告)日：1998-06-02

申请号：US732303

申请日：1997-02-10

申请人： Tetsuo Sotome ,  Takayuki Nakajima ,  Kazutaka Osawa ,  Kazuhiro Shimawaki ,  Kouichi Shiroyama

发明人： Tetsuo Sotome ,  Takayuki Nakajima ,  Kazutaka Osawa ,  Kazuhiro Shimawaki ,  Kouichi Shiroyama

IPC分类号： G01R31/3181 ,  G01R31/319 ,  G06F1/12 ,  G06F11/24 ,  G06F11/273 ,  G06F11/277 ,  H04L1/24 ,  G06F11/00

CPC分类号： G01R31/31813 ,  G01R31/31919 ,  H04L1/241 ,  H04L1/242 ,  G06F11/24

摘要： A bit error measurement system provides means for generating test patterns, multiplexing means and means for specifying and recording a pattern position. In a first aspect, a bit error measurement system has a pattern generator having M channels of pattern generation and a pattern generation controller 10 for controlling the pattern generation in the M channels so that when one channel is selected to generate a pattern the other channels are controlled to be waiting. In a second aspect, a clock frequency difference detector 150 is provided for counting a frequency of an input clock 111 and comparing the results with the frequency at the time of previous switching to detect whether the frequency change is greater than a predetermined value to judge whether the system is in a measurement state and to permit or prohibit a switching operation of a clock switch circuit. In a third aspect, a pattern position recording part 210 is provided to store pattern position information of a reference pattern generator 262 when an error detection signal 265.sub.a is received from a comparator 265.

摘要翻译： PCT No.PCT / JP96 / 00405 Sec。 371日期1997年2月10日 102（e）日期1997年2月10日PCT提交1996年2月22日PCT公布。 公开号WO96 / 26451 日期1996年8月2日位误差测量系统提供用于产生测试图案，复用装置和用于指定和记录图案位置的装置的装置。 在第一方面中，位误差测量系统具有模式生成器，其具有M个模式生成通道，以及模式生成控制器10，用于控制M个通道中的模式生成，使得当选择一个通道以产生模式时，其他通道 控制在等待。 在第二方面，提供时钟频率差检测器150，用于对输入时钟111的频率进行计数，并将结果与​​先前切换时的频率进行比较，以检测频率变化是否大于预定值，以判断是否 系统处于测量状态并且允许或禁止时钟切换电路的切换操作。 在第三方面，当从比较器265接收到错误检测信号265a时，提供图案位置记录部分210以存储参考图案生成器262的图案位置信息。