Abstract:
A system configured to maintain a consistent local-oscillator-power-to-primary-signal-power ratio (LO/SIG ratio). The system may be configured to: receive the voltages for a plurality of optical signal components split from a combined SIG and LO signal; determine individual factors for the plurality of optical signal components; average the individual factors; determine whether the averaged output is less than a minimum reference value for a variable optical attenuator; determine whether the averaged output is greater than a maximum reference value for the variable optical attenuator; change a value associated with the averaged output to the minimum reference value, due to determining that the averaged output is less than the minimum reference value; change a value associated with the averaged output to the maximum reference value, due to determining that the averaged output is greater than the maximum reference value; and change a new value associated with the averaged output to be transmitted to the variable optical attenuator.
Abstract:
This invention relates to a receiver circuit which comprises an equalizer (27) and an error decorrelator (25). The error decorrelator being configured for changing (501; 601, 602) the position of symbols. The invention further relates to a corresponding method. This invention finally relates to an interleaving or deinterleaving method which comprises selecting a first number of symbols (204; 302) within a stream of digital data (13; 28) thereby obtaining selected symbols. The method further comprises exchanging (601, 602) the position of at least half of said first number of symbols of said selected symbols with the position of other symbols from said selected symbols. The invention further relates to an interleaving or deinterleaving circuit.
Abstract:
Phase detection techniques in which an input signal is sampled to obtain several samples at different points in time with respect to a clock, said different points in time comprising an earliest point and latest point. The detection techniques further include generating a phase control signal obtained from the several samples of the input signal.
Abstract:
This invention relates to a phase detection method. An input signal (51, 91, 111) is sampled (13, 14, 15, 16) for obtaining several samples (1, 2, 3) at different points in time which are defined by a clock (C). A phase control signal (4, 5) is obtained (17, 8, 19, 20) form said several samples (1, 2, 3). The phase control signal (4, 5) may be zero, positive or negative. The phase detection method is a rising phase detection method (52; 69; 93, 94), if a zero phase control signal (4) is produced, if a falling slope is detected, or a falling phase detection method (55; 70; 96, 97), if a zero phase control signal (5) is produced, if a rising slope is detected. The invention further relates to a corresponding rising and falling phase detectors, respectively.
Abstract:
Using polarization modulation techniques to simultaneously transmit two different data streams (formatted according to two different protocols) over a single optical wavelength. A first data stream that is encapsulated for transport using a first transport protocol, and a second data stream that is encapsulated for transport using a second transport protocol are received. The first data stream is modulated on a wavelength with a first polarization mode of a polarization division modulation scheme to produce a first modulated data stream and the second data stream is modulated on the wavelength with a second polarization mode of the polarization division multiplex transmission scheme to produce a second modulated data stream having the second polarization mode. The second polarization mode is orthogonal to the first polarization mode. The first and second data streams are combined onto a single wavelength for transmission over a single optical fiber using a polarization beam combiner.
Abstract:
A system configured to maintain a consistent local-oscillator-power-to-primary-signal-power ratio (LO/SIG ratio). The system may be configured to: receive the voltages for a plurality of optical signal components split from a combined SIG and LO signal; determine individual factors for the plurality of optical signal components; average the individual factors; determine whether the averaged output is less than a minimum reference value for a variable optical attenuator; determine whether the averaged output is greater than a maximum reference value for the variable optical attenuator; change a value associated with the averaged output to the minimum reference value, due to determining that the averaged output is less than the minimum reference value; change a value associated with the averaged output to the maximum reference value, due to determining that the averaged output is greater than the maximum reference value; and change a new value associated with the averaged output to be transmitted to the variable optical attenuator.
Abstract:
Carrier phase estimation techniques are provided for processing a received optical signal having a carrier modulated according to a modulation scheme. First and second carrier phase estimation operations are performed on a digital signal derived from an optical carrier obtained from the received optical signal using coherent optical reception. The first carrier phase estimation operation tracks relatively fast phase variations of the optical carrier of the received optical signal to produce a first carrier phase estimation and the second carrier phase estimation operation tracks relatively slow phase variations of the optical carrier of the received optical signal to produce a second carrier phase estimation. A difference between the first and second carrier phase estimations is computed. Occurrence of a cycle slip is determined when the difference is greater than a threshold. A correction is applied to the first carrier phase estimation when the low pass filtered difference exceeds the threshold.
Abstract:
Carrier phase estimation techniques are provided for processing a received optical signal having a carrier modulated according to a modulation scheme. First and second carrier phase estimation operations are performed on a digital signal derived from an optical carrier obtained from the received optical signal using coherent optical reception. The first carrier phase estimation operation tracks relatively fast phase variations of the optical carrier of the received optical signal to produce a first carrier phase estimation and the second carrier phase estimation operation tracks relatively slow phase variations of the optical carrier of the received optical signal to produce a second carrier phase estimation. A difference between the first and second carrier phase estimations is computed. Occurrence of a cycle slip is determined when the difference is greater than a threshold. A correction is applied to the first carrier phase estimation when the low pass filtered difference exceeds the threshold.
Abstract:
This invention relates to a receiver circuit which comprises an equalizer (27) and an error decorrelator (25). The error decorrelator being configured for changing (501; 601, 602) the position of symbols. The invention further relates to a corresponding method. This invention finally relates to an interleaving or deinterleaving method which comprises selecting a first number of symbols (204; 302) within a stream of digital data (13; 28) thereby obtaining selected symbols. The method further comprises exchanging (601, 602) the position of at least half of said first number of symbols of said selected symbols with the position of other symbols from said selected symbols. The invention further relates to an interleaving or deinterleaving circuit.
Abstract:
A clock recovery circuit for use with a high-speed data signal having a low signal to noise ratio is disclosed. The circuit includes a first phase locked loop circuit operating in a fast acquisition mode for acquiring the clock from a data signal, a second phase locked loop circuit for operating in a normal mode to recover the clock signal in the digital data signal once the first phase locked loop circuit has acquired the clock from the data signal, and a switch circuit responsive to switch control signals for switching between the first phase locked loop circuit and the second phase locked loop circuit after the first phase locked loop circuit has acquired the digital data signal.