公开(公告)号：US07149270B2

公开(公告)日：2006-12-12

申请号：US10138210

申请日：2002-05-03

申请人： Claus Dorschky ,  Theodor Kupfer

发明人： Claus Dorschky ,  Theodor Kupfer

IPC分类号： H03D3/24

CPC分类号： H03L7/07 ,  H03L7/095 ,  H03L7/10 ,  H03L7/107 ,  H04L7/0004 ,  H04L7/033

摘要： A clock recovery circuit for use with a high-speed data signal having a low signal to noise ratio is disclosed. The circuit includes a first phase locked loop circuit operating in a fast acquisition mode for acquiring the clock from a data signal, a second phase locked loop circuit for operating in a normal mode to recover the clock signal in the digital data signal once the first phase locked loop circuit has acquired the clock from the data signal, and a switch circuit responsive to switch control signals for switching between the first phase locked loop circuit and the second phase locked loop circuit after the first phase locked loop circuit has acquired the digital data signal.

公开(公告)号：US07095817B2

公开(公告)日：2006-08-22

申请号：US10138212

申请日：2002-05-03

申请人： Claus Dorschky ,  Theodor Kupfer ,  Paul Presslein

发明人： Claus Dorschky ,  Theodor Kupfer ,  Paul Presslein

IPC分类号： H04B7/00

CPC分类号： G06F1/04

摘要： A high-speed digital interface circuit for use with an N bit digital data signal is disclosed. The circuit comprises a source device that initially receives the N bit digital data signal, and a sink device that receives the N bit digital data signal from the source device. The N bit digital data signal has a skew when received by the sink device. A skew detection circuit in the sink device detects the skew in the N bit digital data signal and generates a skew detection signal. A line supplies the skew detection signal to the source device. A compensation circuit in the source device receives the skew detection signal and compensates for the skew in the N bit digital data signal.

公开(公告)号：US5880657A

公开(公告)日：1999-03-09

申请号：US865301

申请日：1997-05-29

申请人： Claus Dorschky ,  Sean Ortiz ,  Kwangsoo Park ,  Roland Seitz ,  David L. Wilson

发明人： Claus Dorschky ,  Sean Ortiz ,  Kwangsoo Park ,  Roland Seitz ,  David L. Wilson

IPC分类号： H01P3/08 ,  H05K1/02 ,  H05K1/18 ,  H05K3/32

CPC分类号： H01P3/081 ,  H05K1/0243 ,  H01L2224/48091 ,  H01L2224/48247 ,  H05K1/0219 ,  H05K1/182 ,  H05K2201/09727 ,  H05K2201/09781 ,  H05K2201/10121 ,  H05K2201/10409 ,  H05K2201/10689 ,  H05K3/0061 ,  H05K3/325

摘要： The propagation of very high frequency signals, e.g., 8 to 10 GHz, via a path printed on a printed wiring board is enhanced by arranging the path so that it simulates a high-quality transmission path at very high frequencies. The path comprises a conventional lead and a series of microstrips, in which the design of the microstrips is optimized to (a) minimize insertion loss and group delay distortion, (b) maximize return loss, and (c) minimize pulse distortion.

摘要翻译： 通过布置路径使得在非常高的频率下模拟高质量传输路径来增强通过印刷在印刷线路板上的路径传播非常高频率信号，例如8至10GHz。 该路径包括常规引线和一系列微带，其中微带的设计被优化为（a）最小化插入损耗和群延迟失真，（b）最大化回波损耗，以及（c）最小化脉冲失真。

公开(公告)号：US07065160B2

公开(公告)日：2006-06-20

申请号：US10042594

申请日：2002-01-09

申请人： Matthias Berger ,  Claus Dorschky ,  Herbert Haunstein ,  Frank Kunz ,  Christoph Schulien ,  Konrad Sticht

发明人： Matthias Berger ,  Claus Dorschky ,  Herbert Haunstein ,  Frank Kunz ,  Christoph Schulien ,  Konrad Sticht

IPC分类号： H03D1/00 ,  H04L27/06

CPC分类号： H03L7/091 ,  H03L7/089 ,  H04L7/033

摘要： A method for correcting the phase of a clock in a data receiver which receives a data flow representing different signal levels with logical high and low signal values and signal transitions positioned therebetween, wherein the positions of such signal transitions between respective two adjacent logical signal values are evaluated for correcting the phase of the clock. The position of a signal transition between a first pair of signal values on one level (11) or a second pair of signal values on the other level (00) is weighted stronger in the evaluation then the positions of signal transitions between adjacent single signal values (1,0) of different signal levels.

摘要翻译： 一种用于校正数据接收机中的时钟相位的方法，该数据接收机接收表示具有逻辑高和低信号值的信号电平的数据流以及位于其间的信号转换，其中相应的两个相邻逻辑信号值之间的这种信号转换的位置是 评估用于校正时钟的相位。 一个电平（11）上的第一对信号值之间的信号转换位置或另一个电平（00）上的第二对信号值在评估中加权得较强，然后在相邻单个信号值之间的信号转换位置 （1,0）不同的信号电平。

公开(公告)号：US06538486B1

公开(公告)日：2003-03-25

申请号：US09686236

申请日：2000-10-11

申请人： Young-Kai Chen ,  Claus Dorschky ,  Carsten Groepper ,  George Georgiou ,  John Mattia ,  Rajasekhar Pullela ,  Mario Reinhold

发明人： Young-Kai Chen ,  Claus Dorschky ,  Carsten Groepper ,  George Georgiou ,  John Mattia ,  Rajasekhar Pullela ,  Mario Reinhold

IPC分类号： H03K3289

CPC分类号： H03K3/287 ,  H03K3/012 ,  H03K3/2885

摘要： A latch chain having improved input voltage sensitivity. The chain includes a first latch, an amplifier, and a second latch connected in series. The second latch is a conventional latch. The first latch is modified to have a higher sensitivity and lower output voltage swing than conventional latches. The modified latch includes a pair of matched output transistors that generate output voltages and a pair of matched biasing circuits to bias the bases of the output transistors with bias voltages. A sample stage is connected so as to apply first biasing currents to one of the biasing circuits in response to input voltages applied to the first latch during the sample period. In addition, a hold stage is connected so as to apply second biasing currents to the biasing circuits during a hold period. The sample and hold stages are configured to apply different voltage differences between the bases of the output transistors.

摘要翻译： 具有改进的输入电压灵敏度的锁存链。 该链包括串联连接的第一锁存器，放大器和第二锁存器。 第二个闩锁是常规的闩锁。 第一个锁存器被修改为具有比传统锁存器更高的灵敏度和更低的输出电压摆幅。 修改的锁存器包括一对匹配的输出晶体管，其产生输出电压和一对匹配的偏置电路，以偏置电压来偏置输出晶体管的基极。 连接样品级，以便响应于在采样周期期间施加到第一锁存器的输入电压，向偏置电路之一施加第一偏置电流。 此外，保持级被连接以便在保持期间向偏置电路施加第二偏置电流。 采样和保持级配置为在输出晶体管的基极之间施加不同的电压差。

公开(公告)号：US06636532B1

公开(公告)日：2003-10-21

申请号：US09375647

申请日：1999-08-17

申请人： Claus Dorschky

发明人： Claus Dorschky

IPC分类号： H04J302

CPC分类号： H04J3/0629 ,  H04J3/047 ,  H04J3/0685 ,  H04L7/0041

摘要： In a network where frequency synchronous lower bit rate signals are combined to form a high bit rate signal by using hierarchies of multiplexers, i.e., concatenated multiplexers of different bit rate levels, an apparatus is provided for adjusting the phase deviations that occur between data input signals and a common clock signal. In one embodiment, the apparatus includes delay lines for delaying the input signals of the multiplexers of the lower hierarchies.

摘要翻译： 在频率同步低比特率信号被组合以通过使用多路复用器的层级（即，不同比特率级别的级联复用器）形成高比特率信号的网络中，提供了一种用于调整在数据输入信号之间发生的相位偏差的装置 和公共时钟信号。 在一个实施例中，该装置包括用于延迟较低层次的多路复用器的输入信号的延迟线。