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公开(公告)号：US07755394B2
公开(公告)日：2010-07-13
申请号：US12196427
申请日：2008-08-22
申请人： Thomas Froehnel , Guenter Mayer , Rolf Sautter , Otto Wagner
发明人： Thomas Froehnel , Guenter Mayer , Rolf Sautter , Otto Wagner
IPC分类号： H03K19/0175
CPC分类号： H03K19/018521 , H03K19/0013
摘要： A circuit (01) combining level shift function with gated reset is described, performing a simple logic function with inputs supplied from a lower voltage (VD) and a drive out at its output (05) with a higher voltage (VC). Said circuit (01) comprises a gated reset scheme plus devices (10, 30, 40) for logic function.
摘要翻译： 描述了将电平移位功能与门控复位组合的电路（01），其具有由较低电压（VD）提供的输入和在其输出端（05）以较高电压（VC）驱动的简单逻辑功能。 所述电路（01）包括门控复位方案加上用于逻辑功能的装置（10,30,40）。
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公开(公告)号：US20130091375A1
公开(公告)日：2013-04-11
申请号：US13269654
申请日：2011-10-10
申请人： Osama Dengler , Thomas Froehnel , Juergen Pille , Rolf Sautter
发明人： Osama Dengler , Thomas Froehnel , Juergen Pille , Rolf Sautter
CPC分类号： G06F17/5031 , G06F1/08 , G06F1/10 , G06F17/5045
摘要： A clock stretcher mechanism is provided for shifting a rising edge of a negative active global clock signal beyond a rising edge of a feedback path signal. A negative active global clock signal and a clock chopper signal are received in a base block. First base block circuitry modifies the clock chopper signal in order to form the feedback path signal. Second base block circuitry shifts the rising edge of the negative active global clock signal beyond the rising edge of the feedback path signal using a delay negative active global clock signal.
摘要翻译： 提供时钟延伸器机构用于将负有效全局时钟信号的上升沿移动超过反馈路径信号的上升沿。 负的有源全局时钟信号和时钟斩波信号被接收在基本块中。 第一基块电路修改时钟斩波信号以形成反馈路径信号。 第二基块电路使用延迟负有源全局时钟信号将负有源全局时钟信号的上升沿移动到反馈路径信号的上升沿。
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公开(公告)号：US20130128684A1
公开(公告)日：2013-05-23
申请号：US13466973
申请日：2012-05-08
摘要： A memory array can be arranged with header devices to reduce leakage. The header devices are coupled with a decoder to receive at least a first portion of a memory address indication and are coupled to receive current from a power supply. Each of header devices is adapted to provide power from the power supply to a set of the wordline drivers corresponding to a bank indicated with the first portion of the memory address indication. Each of the logic devices is coupled to receive at least a second portion of the memory address indication from a decoder. Each of the logic devices is coupled to activate the wordline drivers coupled with those of the wordlines indicated with the second portion of the memory address indication.
摘要翻译： 存储器阵列可以配置有头部装置以减少泄漏。 标题装置与解码器耦合以接收存储器地址指示的至少第一部分，并被耦合以从电源接收电流。 每个头部装置适于从电源向与存储器地址指示的第一部分指示的存储体相对应的一组字线驱动器提供电力。 每个逻辑设备被耦合以从解码器接收存储器地址指示的至少第二部分。 每个逻辑设备被耦合以激活与由存储器地址指示的第二部分指示的字线的字线驱动器耦合的字线驱动器。
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公开(公告)号：US20090058465A1
公开(公告)日：2009-03-05
申请号：US12196427
申请日：2008-08-22
申请人： Thomas Froehnel , Guenter Mayer , Rolf Sautter , Otto Wagner
发明人： Thomas Froehnel , Guenter Mayer , Rolf Sautter , Otto Wagner
IPC分类号： H03K19/0185
CPC分类号： H03K19/018521 , H03K19/0013
摘要： A circuit (01) combining level shift function with gated reset is described, performing a simple logic function with inputs supplied from a lower voltage (VD) and a drive out at its output (05) with a higher voltage (VC). Said circuit (01) comprises a gated reset scheme plus devices (10, 30, 40) for logic function.
摘要翻译： 描述了将电平移位功能与门控复位组合的电路（01），其具有由较低电压（VD）提供的输入和在其输出端（05）以较高电压（VC）驱动的简单逻辑功能。 所述电路（01）包括门控复位方案加上用于逻辑功能的装置（10,30,40）。
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