公开(公告)号：US20130128684A1

公开(公告)日：2013-05-23

申请号：US13466973

申请日：2012-05-08

申请人： Stefan Buettner ,  Thomas Froehnel ,  Werner Juchmes ,  Rolf Sautter ,  Victor Zyuban

发明人： Stefan Buettner ,  Thomas Froehnel ,  Werner Juchmes ,  Rolf Sautter ,  Victor Zyuban

IPC分类号： G11C5/14 ,  G11C8/10

CPC分类号： G11C5/14 ,  G11C8/08 ,  G11C8/10

摘要： A memory array can be arranged with header devices to reduce leakage. The header devices are coupled with a decoder to receive at least a first portion of a memory address indication and are coupled to receive current from a power supply. Each of header devices is adapted to provide power from the power supply to a set of the wordline drivers corresponding to a bank indicated with the first portion of the memory address indication. Each of the logic devices is coupled to receive at least a second portion of the memory address indication from a decoder. Each of the logic devices is coupled to activate the wordline drivers coupled with those of the wordlines indicated with the second portion of the memory address indication.

摘要翻译： 存储器阵列可以配置有头部装置以减少泄漏。 标题装置与解码器耦合以接收存储器地址指示的至少第一部分，并被耦合以从电源接收电流。 每个头部装置适于从电源向与存储器地址指示的第一部分指示的存储体相对应的一组字线驱动器提供电力。 每个逻辑设备被耦合以从解码器接收存储器地址指示的至少第二部分。 每个逻辑设备被耦合以激活与由存储器地址指示的第二部分指示的字线的字线驱动器耦合的字线驱动器。

公开(公告)号：US20090089602A1

公开(公告)日：2009-04-02

申请号：US11862559

申请日：2007-09-27

申请人： Pradip Bose ,  Alper Buyuktosunoglu ,  Chen-Yong Cher ,  Zhigang Hu ,  Hans Jacobson ,  Prabhakar N. Kudva ,  Vijayalakshmi Srinivasan ,  Victor Zyuban

发明人： Pradip Bose ,  Alper Buyuktosunoglu ,  Chen-Yong Cher ,  Zhigang Hu ,  Hans Jacobson ,  Prabhakar N. Kudva ,  Vijayalakshmi Srinivasan ,  Victor Zyuban

IPC分类号： G06F1/28

CPC分类号： G06F1/3287 ,  G06F1/206 ,  G06F9/3836 ,  G06F9/3869 ,  G06F9/5094 ,  Y02D10/16 ,  Y02D10/171 ,  Y02D10/22 ,  Y02D50/20

摘要： A method of power management of a system of connected components includes initializing a token allocation map across the connected components, wherein each component is assigned a power budget as determined by a number of allocated tokens in the token allocation map, monitoring utilization sensor inputs and command state vector inputs, determining, at first periodic time intervals, a current performance level, a current power consumption level and an assigned power budget for the system based on the utilization sensor inputs and the command state vector inputs, and determining, at second periodic time intervals, a token re-allocation map based on the current performance level, the current power consumption level and the assigned power budget for the system, according to a re-assigned power budget of at least one of the connected components, while enforcing a power consumption limit based on a total number of allocated tokens in the system.

摘要翻译： 一种连接组件的系统的电源管理方法包括：在所连接的组件之间初始化令牌分配映射，其中每个组件被分配由令牌分配映射中的分配的令牌数量确定的功率预算，监视利用率传感器输入和命令 状态向量输入，基于所述利用传感器输入和所述命令状态向量输入，以第一周期性时间间隔确定所述系统的当前性能水平，当前功耗级别和所分配的功率预算，以及在所述第二周期时间 间隔，基于当前性能水平的令牌重新分配图，当前功耗水平和系统的分配的功率预算，根据至少一个连接的组件的重新分配的功率预算，同时执行功率 基于系统中分配的令牌总数的消耗限制。

公开(公告)号：US20080168260A1

公开(公告)日：2008-07-10

申请号：US11620790

申请日：2007-01-08

申请人： Victor Zyuban ,  Michael K. Gschwind ,  John-David Wellman

发明人： Victor Zyuban ,  Michael K. Gschwind ,  John-David Wellman

IPC分类号： G06F9/312

CPC分类号： G06F9/3851 ,  G06F9/3838 ,  G06F9/3842

摘要： A method is provided for processing instructions by a processor, in which instructions are queued in an instruction pipeline in a queued order. A first instruction is identified from the queued instructions in the instruction pipeline, the first instruction being identified as having a dependency which is satisfiable within a number of instruction cycles after a current instruction in the instruction pipeline is issued. The first instruction is placed in a side buffer and at least one second instruction is issued from the remaining queued instructions while the first instruction remains in the side buffer. Then, the first instruction is issued from the side buffer after issuing the at least one second instruction in the queued order when the dependency of the first instruction has cleared and after the number of instruction cycles have passed.

摘要翻译： 提供了一种处理器处理指令的方法，其中指令以排队的顺序排队在指令流水线中。 从指令流水线中的排队指令中识别第一指令，第一指令被识别为在发出指令流水线中的当前指令之后的多个指令周期内具有可满足的依赖性。 第一指令被放置在边缓冲器中，并且当第一指令保留在边缓冲器中时，从剩余的排队指令发出至少一个第二指令。 然后，当第一指令的相关性已经清除并且在指令周期数已经过去之后，以排队顺序发出至少一个第二指令之后，从侧缓冲器发出第一指令。

公开(公告)号：US20070220366A1

公开(公告)日：2007-09-20

申请号：US11374871

申请日：2006-03-14

申请人： Pradip Bose ,  Jude Rivers ,  Balaram Sinharoy ,  Victor Zyuban

发明人： Pradip Bose ,  Jude Rivers ,  Balaram Sinharoy ,  Victor Zyuban

IPC分类号： G06F11/00

CPC分类号： G06F11/004 ,  G06F11/3409 ,  G06F2201/88

摘要： A computer implemented method, apparatus, and computer usable program code for preventing soft error accumulation. A number of cycles between references to a register are counted. Instructions are injected that reference the register for preventing soft error accumulation in response to a determination that the number of cycles is greater than a threshold.

摘要翻译： 一种用于防止软错误累积的计算机实现的方法，装置和计算机可用程序代码。 对寄存器的引用之间的一些周期进行计数。 针对响应于循环数大于阈值的确定，注入参考寄存器以防止软错误累积的指令。

公开(公告)号：US20070130237A1

公开(公告)日：2007-06-07

申请号：US11295300

申请日：2005-12-06

申请人： Erik Altman ,  Michael Gschwind ,  Robert Montoye ,  Jude Rivers ,  Sumedh Sathaye ,  John-David Wellman ,  Victor Zyuban

发明人： Erik Altman ,  Michael Gschwind ,  Robert Montoye ,  Jude Rivers ,  Sumedh Sathaye ,  John-David Wellman ,  Victor Zyuban

IPC分类号： G06F17/30

CPC分类号： G06F12/1491 ,  G06F9/3808 ,  G06F9/3844 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/12

摘要： A method and apparatus for storing non-critical processor information without imposing significant costs on a processor design is disclosed. Transient data are stored in the processor-local cache hierarchy. An additional control bit forms part of cache addresses, where addresses having the control bit set are designated as “transient storage addresses.” Transient storage addresses are not written back to external main memory and, when evicted from the last level of cache, are discarded. Preferably, transient storage addresses are “privileged” in that they are either not accessible to software or only accessible to supervisory or administrator-level software having appropriate permissions. A number of management functions/instructions are provided to allow administrator/supervisor software to manage and/or modify the behavior of transient cache storage. This transient storage scheme allows the cache hierarchy to store data items that may be used by the processor core but that may be too expensive to allocate to external memory.

摘要翻译： 公开了一种用于存储非关键处理器信息而不对处理器设计造成重大成本的方法和装置。 瞬态数据存储在处理器本地缓存层次结构中。 附加控制位构成高速缓存地址的一部分，其中具有控制位置位的地址被指定为“瞬时存储地址”。 瞬态存储地址不会被写回外部主存储器，而当从最后一级高速缓存驱逐时，它们将被丢弃。 优选地，瞬态存储地址是“特权的”，因为它们不能被软件访问或只能具有具有适当权限的监督或管理员级软件访问。 提供了许多管理功能/指令，以允许管理员/管理软件管理和/或修改瞬态缓存存储的行为。 这种瞬态存储方案允许高速缓存层级来存储处理器核心可能使用的数据项，但是可能太昂贵以分配给外部存储器。

公开(公告)号：US07051186B2

公开(公告)日：2006-05-23

申请号：US10230492

申请日：2002-08-29

申请人： Sameh Asaad ,  Jaime H. Moreno ,  Victor Zyuban

发明人： Sameh Asaad ,  Jaime H. Moreno ,  Victor Zyuban

IPC分类号： G06F15/82 ,  G06F9/305

CPC分类号： G06F9/3826 ,  G06F9/30109

摘要： A multi-port register file may be selectively bypassed such that any element in a result vector is bypassed to the same index of an input vector of a succeeding operation when the element is requested in the succeeding operation in the same index as it was generated. Alternatively, the results to be placed in a register file may be bypassed to a succeeding operation when the N elements that dynamically compose a vector are requested as inputs to the next operation exactly in the same order as they were generated. That is, for the purposes of bypassing, the N vector elements are treated as a single entity. Similar rules apply for the write-through path.

摘要翻译： 可以选择性地旁路多端口寄存器文件，使得当在跟随生成的相同索引中在后续操作中请求元素时，结果向量中的任何元素被绕过到后续操作的输入向量的相同索引。 或者，当动态组成向量的N个要素作为下一个操作的输入被精确地按照它们被生成的相同顺序被请求作为输入时，放置在寄存器文件中的结果可以被绕过到后续的操作。 也就是说，为了绕过，N个向量元素被视为单个实体。 类似的规则适用于直通路径。

公开(公告)号：US07774654B2

公开(公告)日：2010-08-10

申请号：US12051904

申请日：2008-03-20

申请人： Pradip Bose ,  Jude A. Rivers ,  Balaram Sinharoy ,  Victor Zyuban

发明人： Pradip Bose ,  Jude A. Rivers ,  Balaram Sinharoy ,  Victor Zyuban

IPC分类号： G06F11/00

CPC分类号： G06F11/004 ,  G06F11/3409 ,  G06F2201/88

摘要： A computer implemented method, apparatus, and computer usable program code for preventing soft error accumulation. A number of cycles between references to a register are counted. Instructions are injected that reference the register for preventing soft error accumulation in response to a determination that the number of cycles is greater than a threshold.

摘要翻译： 一种用于防止软错误累积的计算机实现的方法，装置和计算机可用程序代码。 对寄存器的引用之间的一些周期进行计数。 针对响应于循环数大于阈值的确定，注入参考寄存器以防止软错误累积的指令。

公开(公告)号：US07486107B1

公开(公告)日：2009-02-03

申请号：US12123487

申请日：2008-05-20

申请人： Pradip Bose ,  Jeonghee Shin ,  Victor Zyuban

发明人： Pradip Bose ,  Jeonghee Shin ,  Victor Zyuban

IPC分类号： H03K17/16 ,  G05F3/02

CPC分类号： G06F1/3203 ,  G06F1/3296 ,  Y02D10/172

摘要： A method for extending lifetime reliability of CMOS circuitry includes configuring a logic high supply rail, a logic low supply rail, and a virtual supply rail. In an intense recovery mode of operation, a first switching device is rendered nonconductive to isolate the virtual supply rail from the one of the logic high supply rail and the logic low supply rail, and the second switching device is rendered conductive so as to equalize the voltage on the virtual supply rail and the other of the logic high supply rail and the logic low supply rail. At least one device within the circuitry provides one of the logic high voltage and the logic low voltage to a gate terminal of an FET within the circuitry, with a source terminal of the FET coupled to the virtual supply rail, such that the FET is subjected to a reverse bias condition.

摘要翻译： 用于延长CMOS电路的寿命可靠性的方法包括配置逻辑高电源轨，逻辑低电源轨和虚拟电源轨。 在强恢复操作模式中，使第一开关装置不导电以将虚拟电源轨与逻辑高电源轨和逻辑低电源轨之一隔离，并且使第二开关装置导通，以使 虚拟电源线上的电压和逻辑高电源轨和逻辑低电源轨的另一个。 电路内的至少一个器件提供逻辑高电压和逻辑低电压之一到FET内的FET的栅极端子，FET的源极端子连接到虚拟电源轨，使得FET受到 到反向偏置条件。

公开(公告)号：US07461209B2

公开(公告)日：2008-12-02

申请号：US11295300

申请日：2005-12-06

申请人： Erik R. Altman ,  Michael Karl Gschwind ,  Robert Kevin Montoye ,  Jude A. Rivers ,  Sumedh Wasudeo Sathaye ,  John-David Wellman ,  Victor Zyuban

发明人： Erik R. Altman ,  Michael Karl Gschwind ,  Robert Kevin Montoye ,  Jude A. Rivers ,  Sumedh Wasudeo Sathaye ,  John-David Wellman ,  Victor Zyuban

IPC分类号： G06F12/12

CPC分类号： G06F12/1491 ,  G06F9/3808 ,  G06F9/3844 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/12

摘要： A method and apparatus for storing non-critical processor information without imposing significant costs on a processor design is disclosed. Transient data are stored in the processor-local cache hierarchy. An additional control bit forms part of cache addresses, where addresses having the control bit set are designated as “transient storage addresses.” Transient storage addresses are not written back to external main memory and, when evicted from the last level of cache, are discarded. Preferably, transient storage addresses are “privileged” in that they are either not accessible to software or only accessible to supervisory or administrator-level software having appropriate permissions. A number of management functions/instructions are provided to allow administrator/supervisor software to manage and/or modify the behavior of transient cache storage. This transient storage scheme allows the cache hierarchy to store data items that may be used by the processor core but that may be too expensive to allocate to external memory.

摘要翻译： 公开了一种用于存储非关键处理器信息而不对处理器设计造成重大成本的方法和装置。 瞬态数据存储在处理器本地缓存层次结构中。 附加控制位构成高速缓存地址的一部分，其中具有控制位置位的地址被指定为“瞬时存储地址”。 瞬态存储地址不会被写回外部主存储器，而当从最后一级高速缓存驱逐时，它们将被丢弃。 优选地，瞬态存储地址是“特权的”，因为它们不能被软件访问或只能具有具有适当权限的监督或管理员级软件访问。 提供了许多管理功能/指令，以允许管理员/管理软件管理和/或修改瞬态缓存存储的行为。 这种瞬态存储方案允许高速缓存层级来存储处理器核心可能使用的数据项，但是可能太昂贵以分配给外部存储器。

公开(公告)号：US07391233B1

公开(公告)日：2008-06-24

申请号：US11928232

申请日：2007-10-30

申请人： Pradip Bose ,  Jeonghee Shin ,  Victor Zyuban

发明人： Pradip Bose ,  Jeonghee Shin ,  Victor Zyuban

IPC分类号： H03K17/16 ,  G05F3/02

CPC分类号： G06F1/3203 ,  G06F1/3296 ,  H03K19/0016 ,  Y02D10/172

摘要： An apparatus for extending lifetime reliability of CMOS circuitry includes a first switching device between a logic high supply rail/logic low supply rail, and a virtual supply rail coupled to the CMOS circuitry. In a first mode of operation the first switching device supplies the full voltage value between the logic high supply rail and the logic low supply rail, and in a second mode of operation, the first switching device isolates the virtual supply rail from the logic high supply rail/logic low supply rail, thereby reducing the voltage supplied to the CMOS circuitry. A second switching device coupled between the virtual supply rail and the logic low supply rail/logic high supply rail, in a third mode of operation, equalizes the voltage on the virtual supply rail and the logic low supply rail/logic high supply rail.

摘要翻译： 用于延长CMOS电路的寿命可靠性的装置包括在逻辑高电源轨/逻辑低电源轨和耦合到CMOS电路的虚拟电源轨之间的第一开关器件。 在第一操作模式中，第一开关装置在逻辑高电源轨和逻辑低电源轨之间提供全电压值，并且在第二操作模式中，第一开关装置将虚拟供电轨与逻辑高电源 轨/逻辑低电源轨，从而降低供应给CMOS电路的电压。 耦合在虚拟电源轨和逻辑低电源轨/逻辑高电源轨之间的第二开关装置，在第三操作模式下，使虚拟电源轨和逻辑低电源轨/逻辑高电源轨的电压相等。