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6 条记录 (耗时 0.011 秒)

    Digital magnetic read channel and method
    2.
    发明授权
    Digital magnetic read channel and method 失效
    数字磁读通道及方法

    公开(公告)号：US6049478A

    公开(公告)日：2000-04-11

    申请号：US262405

    申请日：1999-03-04

    申请人： Thomas M Walley ,  Jacob L. Bell ,  William L. Pherigo, Jr.

    发明人： Thomas M Walley ,  Jacob L. Bell ,  William L. Pherigo, Jr.

    IPC分类号： G06K17/00 ,  G06K7/016 ,  G06K7/08 ,  G11B5/02 ,  G11B5/09 ,  G11B20/10 ,  G11C7/00

    CPC分类号： G06K7/084 ,  G06K7/016

    摘要： Disclosed is a system and method for generating a data sequence from a two frequency coherent phase signal. The system comprises an integrated magnetic read channel that includes a magnetic reader circuit configured to generate an analog two frequency coherent phase (F2F) signal from a magnetic strip, the analog F2F signal having a number of alternating positive and negative peaks having a respective positive and negative transitions therebetween. The output of the magnetic reader circuit is applied to an analog-to-digital converter configured to convert the analog F2F signal into a digital F2F signal. Thereafter, the digital F2F signal is applied to a peak detector configured to identify the alternating negative and positive peaks. The magnetic read channel also includes a transition calculator configured to determine a transition time between each of the consecutively positioned alternating positive and negative peaks, and a frequency locked loop configured to determine a transition type for each of the transition times. Finally, the output of the frequency locked loop is applied to a data separator configured to determine a data value from the transition types.

    摘要翻译： 公开了一种用于从双频相干相位信号产生数据序列的系统和方法。 该系统包括集成磁读取通道，其包括被配置为从磁条产生模拟两相位相位相位（F2F）信号的磁读取器电路，模拟F2F信号具有多个交替的正和负峰值，其具有相应的正和 其间的负变换。 磁读取器电路的输出被应用于被配置为将模拟F2F信号转换为数字F2F信号的模拟 - 数字转换器。 此后，数字F2F信号被施加到配置成识别交替的负峰值和正峰值的峰值检测器。 磁读取通道还包括转移计算器，其被配置为确定每个连续定位的交替正和负峰值之间的转换时间，以及被配置为确定每个转换时间的转换类型的频率锁定回路。 最后，频率锁定循环的输出被应用于配置为从转换类型确定数据值的数据分离器。

    Apparatus and method for three-dimensional relative movement sensing
    3.
    发明授权
    Apparatus and method for three-dimensional relative movement sensing 有权
    三维相对运动检测装置及方法

    公开(公告)号：US06770863B2

    公开(公告)日：2004-08-03

    申请号：US10004512

    申请日：2001-10-26

    申请人： Thomas M. Walley

    发明人： Thomas M. Walley

    IPC分类号： G06M700

    CPC分类号： G06F3/0346 ,  G01B11/002 ,  G06F3/0304

    摘要： An apparatus for sensing three-dimensional relative movement includes a movable motion sensor including a first and a second two-dimensional array of photo detectors. At least one lens directs far-field images onto the first and the second arrays of photo detectors. The sensor is configured to generate digital representations of the far-field images and to generate three-dimensional relative movement data based on the digital representations of the far-field images. The movement data is indicative of motion of the sensor in three dimensions.

    摘要翻译： 用于感测三维相对运动的装置包括可移动运动传感器，其包括光电检测器的第一和第二二维阵列。 至少一个透镜将远场图像引导到第一和第二光电检测器阵列上。 传感器被配置为生成远场图像的数字表示，并且基于远场图像的数字表示来生成三维相对运动数据。 运动数据表示三维传感器的运动。

    Accurate time delay system and method utilizing an inaccurate oscillator
    4.
    发明授权
    Accurate time delay system and method utilizing an inaccurate oscillator 失效
    精确的延时系统和方法利用不准确的振荡器

    公开(公告)号：US06326825B1

    公开(公告)日：2001-12-04

    申请号：US09765188

    申请日：2001-01-18

    申请人： Thomas M Walley

    发明人： Thomas M Walley

    IPC分类号： H03L700

    CPC分类号： H03L1/00 ,  H03L7/00

    摘要： A time delay system and method utilize an accurate clock signal with a known frequency to calibrate an inaccurate clock signal that will be used to generate a desired time delay. In the case that the frequency of the inaccurate clock signal is lower than the frequency of the accurate clock signal, the number of cycles of the accurate clock signal that occur during a predetermined portion of the inaccurate clock signal is used to calibrate the inaccurate clock signal. Alternately, if the frequency of the inaccurate clock signal is higher than the frequency of the accurate clock signal, the number of cycles of the inaccurate clock signal that occur during a predetermined portion of the accurate clock signal is used in the calibration. The calibrated inaccurate clock signal is then utilized to generate an accurate time delay.

    摘要翻译： 时间延迟系统和方法利用具有已知频率的精确时钟信号来校准将用于产生所需时间延迟的不准确的时钟信号。 在不准确的时钟信号的频率低于精确时钟信号的频率的情况下，在不精确的时钟信号的预定部分期间发生的精确时钟信号的周期数用于校准不准确的时钟信号 。 或者，如果不准确的时钟信号的频率高于精确时钟信号的频率，则在校准中使用在精确时钟信号的预定部分期间发生的不准确的时钟信号的周期数。 然后利用经校准的不准确时钟信号产生准确的时间延迟。

    CMOS peak amplitude detector
    6.
    发明授权
    CMOS peak amplitude detector 失效
    CMOS峰值检波器

    公开(公告)号：US5302863A

    公开(公告)日：1994-04-12

    申请号：US11028

    申请日：1993-01-29

    申请人： Thomas M. Walley ,  Larry S. Metz ,  Charles E. Moore

    发明人： Thomas M. Walley ,  Larry S. Metz ,  Charles E. Moore

    IPC分类号： G01R19/04 ,  G11C27/00 ,  G11C27/02 ,  H03K5/1532 ,  H03K5/153

    CPC分类号： H03K5/1532 ,  G01R19/04 ,  G11C27/00 ,  G11C27/026

    摘要： A fully-integrated CMOS peak detector stores the peak amplitude of an input signal using an on-chip storage capacitor. The fully-integrated CMOS peak detector includes a delay buffer, a transfer gate and a comparator. A discharge controller is used to step-down the peak amplitude stored on the on-chip storage capacitor some predetermined amount. The discharge controller includes a switched capacitor circuit which is placed in series with the storage capacitor such that the two capacitors act as a capacitive voltage divider to produce a predictable fraction of the acquired peak amplitude. Multiple peaks can be determined and/or stored by using multiple fully-integrated CMOS peak detectors in conjunction with a single comparator. A multiplexer is used in this configuration to control the multiple peak detectors.

    摘要翻译： 全集成CMOS峰值检测器使用片上存储电容器存储输入信号的峰值幅度。 完全集成的CMOS峰值检测器包括延迟缓冲器，传输门和比较器。 放电控制器用于降低存储在片上存储电容器上的峰值幅度一定的量。 放电控制器包括与存储电容器串联放置的开关电容器电路，使得两个电容器用作电容分压器以产生所获取的峰值幅度的可预测分数。 可以通过结合单个比较器使用多个完全集成的CMOS峰值检测器来确定和/或存储多个峰。 在该配置中使用多路复用器来控制多个峰值检测器。