公开(公告)号：US20110228823A1

公开(公告)日：2011-09-22

申请号：US12725399

申请日：2010-03-16

申请人： Robert C. Lutz ,  Thomas S. Wong ,  Klaus P. Piontek

发明人： Robert C. Lutz ,  Thomas S. Wong ,  Klaus P. Piontek

IPC分类号： H04B3/00 ,  H04B1/38

CPC分类号： H04B3/141

摘要： A transmission line pre-emphasis circuit includes a primary signal path receiving a digital data stream and generating a primary output current indicative of the digital data stream, one or more secondary signal paths each incorporating a network implementing a specific transient response where the one or more secondary signal paths receive the digital data stream and generate secondary output currents representing one or more overshoot signals indicative of the transient response of the respective network. The one or more secondary signal paths have variable gain being programmed through respective DC programming signals. The secondary output currents are summed with the primary output current. The transmission line pre-emphasis circuit further includes an output loading stage coupled to generate from the summed current a pre-emphasized digital output signal indicative of the one or more overshoot signals added to the digital data stream.

摘要翻译： 传输线预加重电路包括接收数字数据流并且产生指示数字数据流的主要输出电流的主信号路径，每一个包含实现特定瞬态响应的网络的辅助信号路径，其中一个或多个 次级信号路径接收数字数据流并产生代表表示相应网络的瞬态响应的一个或多个过冲信号的次级输出电流。 一个或多个辅助信号路径具有通过相应的DC编程信号编程的可变增益。 次级输出电流与初级输出电流相加。 传输线预加重电路还包括输出加载级，其耦合以从总和电流产生指示加到数字数据流的一个或多个过冲信号的预加重数字输出信号。

公开(公告)号：US20100253385A1

公开(公告)日：2010-10-07

申请号：US12420006

申请日：2009-04-07

申请人： Thomas S. Wong ,  Vincent Stueve

发明人： Thomas S. Wong ,  Vincent Stueve

IPC分类号： H03K19/003

CPC分类号： H03K5/003 ,  H03K5/08 ,  H03K5/151

摘要： A digital signal detector detects digital signals by only sensing the rising and falling edges of a received digital signal and latches the logic state between the detected edges. Such edges contain very high frequencies that are much higher than the fundamental frequency of the digital signal train. A small high pass filter filters out at least the DC component and the fundamental frequency of the received digital signal. A filtered edge appears as a spike that goes either positive or negative depending on whether the edge is a rising or falling edge. A memory element, such as comprising an RS flip flop, is triggered by the positive and negative spikes. A positive spike triggers the flip flop to output a logical one, and a negative spike triggers the latch to output a logical zero. In this way, the digital signal is recreated without the original digital signal itself being required to pass through the high pass filter.

摘要翻译： 数字信号检测器通过仅感测接收的数字信号的上升沿和下降沿来检测数字信号，并锁存检测到的边缘之间的逻辑状态。 这样的边缘包含比数字信号列的基频高得多的非常高的频率。 小的高通滤波器至少滤除接收到的数字信号的直流分量和基频。 根据边沿是上升沿还是下降沿，滤波后的边沿显示为正或负的尖峰。 诸如包括RS触发器的存储元件由正和负尖峰触发。 正尖峰触发触发器输出逻辑1，负尖峰触发锁存器输出逻辑0。 以这种方式，重新创建数字信号，而不需要原始数字信号通过高通滤波器。

公开(公告)号：US20090138742A1

公开(公告)日：2009-05-28

申请号：US11946816

申请日：2007-11-28

申请人： Thomas S. Wong ,  Ulrich Bruedigam

发明人： Thomas S. Wong ,  Ulrich Bruedigam

IPC分类号： G06F1/12

CPC分类号： G06F5/06

摘要： A circuit is described for automatically adjusting a phase of an input register load clock to be synchronized with transitions of data bits forming an n-bit word. The circuit detects the first transition of a data bit in the n-bit word. The circuit then time-shifts the input clock, to generate a shifted clock, so that a triggering edge of the shifted clock occurs sometime after generation of the transition detect signal, such as in the middle third of a data cycle. Shifting the input clock may be performed by multiplying the input clock to generate a plurality of sub-clock cycles and selecting one of the sub-clock cycles as the start of the shifted clock cycle. The parallel data are applied to inputs of input registers clocked using the shifted clock as the load clock. Thus, the load clock occurs at an optimum time near the middle of a data cycle.

摘要翻译： 描述了用于自动调整输入寄存器加载时钟的相位以与与形成n位字的数据位的转变同步的电路。 该电路检测n位字中数据位的第一次转换。 然后，电路对输入时钟进行时移，以产生移位的时钟，使得移位时钟的触发沿在诸如数据周期的三分之一的转换检测信号生成之后的某个时刻发生。 可以通过将输入时钟相乘以产生多个子时钟周期并选择一个子时钟周期作为移位的时钟周期的开始来执行移位输入时钟。 并行数据被应用到使用移位时钟作为负载时钟的输入寄存器的输入。 因此，负载时钟发生在接近数据周期中间的最佳时间。

公开(公告)号：US07443008B2

公开(公告)日：2008-10-28

申请号：US11419558

申请日：2006-05-22

申请人： Robert C. Lutz ,  Thomas S. Wong

发明人： Robert C. Lutz ,  Thomas S. Wong

IPC分类号： H01L29/00

CPC分类号： H01L21/84 ,  G11C17/16 ,  H01L27/11801 ,  H01L27/1203 ,  H01L29/868 ,  Y10S257/91

摘要： A programmable element includes a diode and a programmable structure formed in a polysilicon layer isolated from a semiconductor substrate by a dielectric layer. The diode includes a first region and a second region of opposite conductivity types. The programmable structure includes a third region and a fourth region of opposite conductivity types. The first region of the diode and the third region of the programmable structure are electrically connected. In operation, the programmable structure is programmed to a low impedance state when a voltage exceeding a first breakdown voltage of the programmable structure is applied to reverse bias the programmable structure. The programmable element can be used to form a programmable array having very low parasitic capacitance, enabling the realization of a large and ultra fast programmable logic array.

摘要翻译： 可编程元件包括形成在通过电介质层与半导体衬底隔离的多晶硅层中的二极管和可编程结构。 二极管包括第一区域和相反导电类型的第二区域。 可编程结构包括具有相反导电类型的第三区域和第四区域。 二极管的第一区域和可编程结构的第三区域电连接。 在操作中，当施加超过可编程结构的第一击穿电压的电压以将可编程结构反向偏置时，可编程结构被编程为低阻抗状态。 可编程元件可用于形成具有非常低的寄生电容的可编程阵列，使得能够实现大型和超快速可编程逻辑阵列。

公开(公告)号：US20080068064A1

公开(公告)日：2008-03-20

申请号：US11523362

申请日：2006-09-18

申请人： Thomas S. Wong

发明人： Thomas S. Wong

IPC分类号： H03K17/16

CPC分类号： H03K19/01812 ,  H03F3/45085 ,  H03F2203/45352 ,  H03F2203/45702 ,  H03K17/60

摘要： An input buffer circuit. In one embodiment, the input buffer circuit includes a first transistor operable to receive a first input signal, a second transistor operable to receive a second input signal, and a first mechanism coupled to the first transistor and to the second transistor. The first mechanism is operable to control the first and second transistors such that the first and second transistors can receive either single-ended input signals or differential input signals. According to the embodiments disclosed herein, the input buffer combines single-ended input and differential input functionalities without compromising performance.

摘要翻译： 输入缓冲电路。 在一个实施例中，输入缓冲电路包括可操作以接收第一输入信号的第一晶体管，可操作以接收第二输入信号的第二晶体管，以及耦合到第一晶体管和第二晶体管的第一机构。 第一机构可操作以控制第一和第二晶体管，使得第一和第二晶体管可以接收单端输入信号或差分输入信号。 根据本文公开的实施例，输入缓冲器组合单端输入和差分输入功能而不影响性能。

公开(公告)号：US4740971A

公开(公告)日：1988-04-26

申请号：US835078

申请日：1986-02-28

申请人： Aloysius T. Tam ,  Thomas S. Wong ,  Jim L. Michelsen ,  David F. Naren ,  David Wang

发明人： Aloysius T. Tam ,  Thomas S. Wong ,  Jim L. Michelsen ,  David F. Naren ,  David Wang

IPC分类号： G06F11/22 ,  G06F11/10 ,  G06F11/267 ,  G06F12/08 ,  G06F12/16 ,  G11C29/00 ,  G11C29/24 ,  G11C29/42 ,  G01R31/28

CPC分类号： G11C29/835 ,  G06F11/1064 ,  G11C29/24 ,  G11C29/42 ,  G06F11/2215

摘要： A tag buffer having built-in testing capabilities is disclosed. In a single-chip, integrated-circuit design which includes a SRAM, a parity generator and checker, and a comparator, a method and capability of testing the functionality of the SRAM and parity components is defined. For an embodiment in which the SRAM component includes a redundancy scheme for replacing a defective memory array row, a test for determining whether a redundant row has been used is also provided.

摘要翻译： 公开了具有内置测试能力的标签缓冲器。 在包括SRAM，奇偶校验发生器和检验器以及比较器的单片式集成电路设计中，定义了测试SRAM和奇偶校验元件的功能的方法和能力。 对于其中SRAM组件包括用于替换有缺陷的存储器阵列行的冗余方案的实施例，还提供了用于确定是否已经使用冗余行的测试。

公开(公告)号：US08861584B2

公开(公告)日：2014-10-14

申请号：US13587639

申请日：2012-08-16

申请人： George W. Brown ,  Thomas S. Wong ,  Bernd Neumann

发明人： George W. Brown ,  Thomas S. Wong ,  Bernd Neumann

IPC分类号： H03K7/04 ,  H03K7/06 ,  H03K9/04 ,  H03K9/06 ,  H03K7/00 ,  H03K5/19

CPC分类号： H03K5/19 ,  H03K5/1252 ,  H03K7/00 ,  H04B10/695

摘要： A noise discriminator circuit and a noise discrimination method in a burst mode receiver is configured to determine the validity of an incoming burst signal by analyzing the timing of the signal edges of incoming signal to look for a time duration conforming to the preamble data bits of a valid burst signal. In one embodiment, the noise discriminator circuit and method analyze the time duration between signal edges of the same pulse of an incoming signal. In another embodiment, the noise discriminator circuit and method analyze the time duration between a first set of pulses of an incoming signal and the time duration between signal edges of a second set of pulses of the incoming signal. When the time durations are within a given time range relating to a predetermined timing separation of a valid burst signal, the incoming signal is validated as a valid burst signal.

摘要翻译： 突发模式接收机中的噪声鉴别器电路和噪声识别方法被配置为通过分析输入信号的信号边沿的定时来确定输入突发信号的有效性，以寻找符合一个 有效突发信号。 在一个实施例中，噪声识别器电路和方法分析输入信号的相同脉冲的信号边沿之间的持续时间。 在另一个实施例中，噪声鉴别器电路和方法分析入射信号的第一组脉冲与输入信号的第二组脉冲的信号沿之间的持续时间之间的持续时间。 当持续时间在与有效突发信号的预定时间间隔相关的给定时间范围内时，输入信号被验证为有效的突发信号。

公开(公告)号：US20130279903A1

公开(公告)日：2013-10-24

申请号：US13587662

申请日：2012-08-16

申请人： George W. Brown ,  Thomas S. Wong ,  Bernd Neumann

发明人： George W. Brown ,  Thomas S. Wong ,  Bernd Neumann

IPC分类号： H04B10/06 ,  H03K5/19 ,  H04B17/00

CPC分类号： H03K5/19 ,  H03K5/1252 ,  H03K7/00 ,  H04B10/695

摘要： A noise discriminator circuit and a noise discrimination method in a burst mode receiver is configured to determine the validity of an incoming burst signal by analyzing the timing of the signal edges of incoming signal to look for a time duration conforming to the preamble data bits of a valid burst signal. In one embodiment, the noise discriminator circuit and method analyze the time duration between signal edges of the same pulse of an incoming signal. In another embodiment, the noise discriminator circuit and method analyze the time duration between a first set of pulses of an incoming signal and the time duration between signal edges of a second set of pulses of the incoming signal. When the time durations are within a given time range relating to a predetermined timing separation of a valid burst signal, the incoming signal is validated as a valid burst signal.

摘要翻译： 突发模式接收机中的噪声鉴别器电路和噪声识别方法被配置为通过分析输入信号的信号边沿的定时来确定输入突发信号的有效性，以寻找符合一个 有效突发信号。 在一个实施例中，噪声识别器电路和方法分析输入信号的相同脉冲的信号边沿之间的持续时间。 在另一个实施例中，噪声鉴别器电路和方法分析入射信号的第一组脉冲与输入信号的第二组脉冲的信号沿之间的持续时间之间的持续时间。 当持续时间在与有效突发信号的预定时间间隔相关的给定时间范围内时，输入信号被验证为有效的突发信号。

公开(公告)号：US08295336B2

公开(公告)日：2012-10-23

申请号：US12725399

申请日：2010-03-16

申请人： Robert C. Lutz ,  Thomas S. Wong ,  Klaus P. Piontek

发明人： Robert C. Lutz ,  Thomas S. Wong ,  Klaus P. Piontek

IPC分类号： H04B1/38

CPC分类号： H04B3/141

摘要： A transmission line pre-emphasis circuit includes a primary signal path receiving a digital data stream and generating a primary output current indicative of the digital data stream, one or more secondary signal paths each incorporating a network implementing a specific transient response where the one or more secondary signal paths receive the digital data stream and generate secondary output currents representing one or more overshoot signals indicative of the transient response of the respective network. The one or more secondary signal paths have variable gain being programmed through respective DC programming signals. The secondary output currents are summed with the primary output current. The transmission line pre-emphasis circuit further includes an output loading stage coupled to generate from the summed current a pre-emphasized digital output signal indicative of the one or more overshoot signals added to the digital data stream.

摘要翻译： 传输线预加重电路包括接收数字数据流并且产生指示数字数据流的主要输出电流的主信号路径，每一个包含实现特定瞬态响应的网络的辅助信号路径，其中一个或多个 次级信号路径接收数字数据流并产生代表表示相应网络的瞬态响应的一个或多个过冲信号的次级输出电流。 一个或多个辅助信号路径具有通过相应的DC编程信号编程的可变增益。 次级输出电流与初级输出电流相加。 传输线预加重电路还包括输出加载级，其耦合以从总和电流产生指示加到数字数据流的一个或多个过冲信号的预加重数字输出信号。

公开(公告)号：US08138851B2

公开(公告)日：2012-03-20

申请号：US12725394

申请日：2010-03-16

申请人： Robert C. Lutz ,  Thomas S. Wong ,  Ulrich Bruedigam

发明人： Robert C. Lutz ,  Thomas S. Wong ,  Ulrich Bruedigam

IPC分类号： H04B3/14

CPC分类号： H04B3/145 ,  H04L25/0274 ,  H04L25/0284 ,  H04L25/0286 ,  H04L25/03885

摘要： A transmission line equalizer includes multiple signal paths connected in parallel between an equalizer input signal and an output amplifier where each signal path has a network implementing a specific frequency dependent response and each signal path implements current gain amplification with one or more of the signal paths having a variable gain programmed through a time invariant, DC programming signal. Furthermore, one or more of the signal paths implements linear-to-nonlinear signal transformations and compensating nonlinear-to-linear signal transformations to generate linearized output signals at the one or more signal paths. The equalizer further includes the output amplifier summing output signals from the multiple signal paths to generate an equalized output signal. In operation, the gain of the one or more signal paths is varied to establish the relative proportions of the output signals generated by each signal path and summed at the output amplifier.

摘要翻译： 传输线均衡器包括在均衡器输入信号和输出放大器之间并联连接的多个信号路径，其中每个信号路径具有实现特定频率相关响应的网络，并且每个信号路径通过具有一个或多个信号路径来实现电流增益放大， 通过时变不变的DC编程信号编程的可变增益。 此外，一个或多个信号路径实现线性到非线性的信号变换，并补偿非线性到线性的信号变换，以在一个或多个信号路径上产生线性化的输出信号。 均衡器还包括输出放大器对来自多个信号路径的输出信号求和以产生均衡的输出信号。 在操作中，改变一个或多个信号路径的增益以建立由每个信号路径产生并在输出放大器相加的输出信号的相对比例。