公开(公告)号：US20100119024A1

公开(公告)日：2010-05-13

申请号：US12688617

申请日：2010-01-15

Applicant: Sergey Y. Shumarayev ,  Rakesh H. Patel ,  Wilson Wong ,  Tim T. Hoang

Inventor： Sergey Y. Shumarayev ,  Rakesh H. Patel ,  Wilson Wong ,  Tim T. Hoang

IPC: H04L7/00

CPC classification number: H03L7/0998 ,  H03L7/081 ,  H03L7/087 ,  H03L7/113 ,  H03L7/14 ,  H04L7/0025 ,  H04L7/0083 ,  H04L7/033

Abstract: The disclosed invention is a technology for producing a recovered clock signal using a multi-mode clock data recovery (CDR) circuit that accommodates a flexible range operating frequencies F and consecutive identical digit requirements CID. In a first mode of operation, a controlled oscillator produces the recovered clock signal, and in a second mode of operation, a phase interpolator produces the recovered clock signal. The multi-mode CDR circuit operates in the first mode if (CID/F) is less than a threshold time value and in the second mode if (CID/F) is greater than the threshold time value.

Abstract translation: 所公开的发明是使用容纳灵活范围操作频率F和连续相同数字要求CID的多模式时钟数据恢复（CDR）电路产生恢复的时钟信号的技术。 在第一操作模式中，受控振荡器产生恢复的时钟信号，并且在第二操作模式中，相位内插器产生恢复的时钟信号。 （CID / F）小于阈值时间值，如果（CID / F）大于阈值时间值，则多模式CDR电路以第一模式工作。

公开(公告)号：US07680232B2

公开(公告)日：2010-03-16

申请号：US11040342

申请日：2005-01-21

Applicant: Sergey Y Shumarayev ,  Rakesh H Patel ,  Wilson Wong ,  Tim T Hoang

Inventor： Sergey Y Shumarayev ,  Rakesh H Patel ,  Wilson Wong ,  Tim T Hoang

IPC: H04L7/00 ,  H03D3/24

CPC classification number: H03L7/0998 ,  H03L7/081 ,  H03L7/087 ,  H03L7/113 ,  H03L7/14 ,  H04L7/0025 ,  H04L7/0083 ,  H04L7/033

Abstract: The disclosed invention is a technology for producing a recovered clock signal using a multi-mode clock data recovery (CDR) circuit that accommodates a flexible range operating frequencies F and consecutive identical digit requirements CID. In a first mode of operation, a controlled oscillator produces the recovered clock signal, and in a second mode of operation, a phase interpolator produces the recovered clock signal. The multi-mode CDR circuit operates in the first mode if (CID/F) is less than a threshold time value and in the second mode if (CID/F) is greater than the threshold time value.

Abstract translation: 所公开的发明是使用容纳灵活范围操作频率F和连续相同数字要求CID的多模式时钟数据恢复（CDR）电路产生恢复的时钟信号的技术。 在第一操作模式中，受控振荡器产生恢复的时钟信号，并且在第二操作模式中，相位内插器产生恢复的时钟信号。 （CID / F）小于阈值时间值，如果（CID / F）大于阈值时间值，则多模式CDR电路以第一模式工作。

公开(公告)号：US07304494B2

公开(公告)日：2007-12-04

申请号：US11098832

申请日：2005-04-04

Applicant: Wilson Wong ,  Tim T Hoang ,  Sergey Y Shumarayev ,  Rakesh H Patel ,  Simardeep Maangat

Inventor： Wilson Wong ,  Tim T Hoang ,  Sergey Y Shumarayev ,  Rakesh H Patel ,  Simardeep Maangat

IPC: H03K17/16

CPC classification number: H03K19/017545

Abstract: Circuitry and methods are provided for an LVDS-like transmitter that may be able to DC couple to a receiver having a CML termination scheme. Replacing the common mode voltage source of an LVDS transmitter with a resistive pulldown to ground may allow the transmitter to interface in a DC coupled fashion with a CML receiver. Further, the resistive pulldown may be programmable. This LVDS-like transmitter may be able to support a wider customer base by allowing it to DC couple to a wider range of termination voltage levels, such as CML termination voltage levels.

Abstract translation: 为能够将DC耦合到具有CML终止方案的接收机的类似LVDS的发射机提供电路和方法。 将具有电阻下拉到地的LVDS发射机的共模电压源替换可允许发射机以直流耦合方式与CML接收器接口。 此外，电阻下拉可以是可编程的。 这种类似LVDS的发射机可能能够通过允许其将DC耦合到更广泛的终止电压电平范围（例如CML终止电压电平）来支持更广泛的客户群。

公开(公告)号：US07242221B1

公开(公告)日：2007-07-10

申请号：US11056442

申请日：2005-02-11

Applicant: Tim T Hoang ,  Sergey Y Shumarayev ,  Wilson Wong ,  Simardeep Maangat

Inventor： Tim T Hoang ,  Sergey Y Shumarayev ,  Wilson Wong ,  Simardeep Maangat

IPC: H03K19/0175

CPC classification number: H03K19/017581

Abstract: Programmable logic device circuitry for receiving and/or transmitting a differential signal includes controllable invert circuitry that effectively reverses the polarity of the differential signal. The controllable invert circuitry operates on a single-ended (non-differential) signal that has either been derived from a differential input signal or from which a differential output signal will be derived.

Abstract translation: 用于接收和/或发送差分信号的可编程逻辑器件电路包括有效地反转差分信号极性的可控逆变电路。 可控逆变电路对已经从差分输入信号导出的差分输出信号或从其导出差分输出信号的单端（非差分）信号进行操作。

公开(公告)号：US07411464B1

公开(公告)日：2008-08-12

申请号：US11430469

申请日：2006-05-08

Applicant: Tim T Hoang ,  Sergey Shumarayev

Inventor： Tim T Hoang ,  Sergey Shumarayev

IPC: H03B5/24 ,  H03L1/00 ,  H03L7/099

CPC classification number: H03K5/1565 ,  H03K3/0315 ,  H03L7/18

Abstract: An oscillator circuit can generate a periodic signal, and a frequency adjustment circuit can adjust the frequency of the periodic signal. The periodic signal may include phase jitter. In one aspect of the invention, the phase jitter may be mitigated by connecting other circuitry to the oscillator circuit and allowing the other circuitry to draw current. In one embodiment, the other circuitry is connected in parallel with the oscillator circuit. In one embodiment, the other circuitry is configured to draw greater current to mitigate more phase jitter and to draw less current to mitigate less phase jitter. In one embodiment, a greater portion of the other circuitry is connected to the oscillator circuit for higher frequencies and a lesser portion of the other circuitry is connected to the oscillator circuit for lower frequencies.

Abstract translation: 振荡器电路可以产生周期信号，并且频率调节电路可以调节周期信号的频率。 周期信号可能包括相位抖动。 在本发明的一个方面，通过将其它电路连接到振荡器电路并允许其它电路抽取电流可以减轻相位抖动。 在一个实施例中，另一个电路与振荡器电路并联连接。 在一个实施例中，另一个电路被配置为绘制更大的电流以减轻更多的相位抖动并绘制更少的电流以减轻较少的相位抖动。 在一个实施例中，其他电路的较大部分连接到振荡器电路用于较高频率，而另一电路的较小部分连接到用于较低频率的振荡器电路。

公开(公告)号：US08537954B2

公开(公告)日：2013-09-17

申请号：US12688617

申请日：2010-01-15

Applicant: Sergey Y. Shumarayev ,  Rakesh H. Patel ,  Wilson Wong ,  Tim T. Hoang

Inventor： Sergey Y. Shumarayev ,  Rakesh H. Patel ,  Wilson Wong ,  Tim T. Hoang

IPC: H03D3/24

CPC classification number: H03L7/0998 ,  H03L7/081 ,  H03L7/087 ,  H03L7/113 ,  H03L7/14 ,  H04L7/0025 ,  H04L7/0083 ,  H04L7/033

Abstract: The disclosed invention is a technology for producing a recovered clock signal using a multi-mode clock data recovery (CDR) circuit that accommodates a flexible range operating frequencies F and consecutive identical digit requirements CID. In a first mode of operation, a controlled oscillator produces the recovered clock signal, and in a second mode of operation, a phase interpolator produces the recovered clock signal. The multi-mode CDR circuit operates in the first mode if (CID/F) is less than a threshold time value and in the second mode if (CID/F) is greater than the threshold time value.

Abstract translation: 所公开的发明是使用容纳灵活范围操作频率F和连续相同数字要求CID的多模式时钟数据恢复（CDR）电路产生恢复的时钟信号的技术。 在第一操作模式中，受控振荡器产生恢复的时钟信号，并且在第二操作模式中，相位内插器产生恢复的时钟信号。 （CID / F）小于阈值时间值，如果（CID / F）大于阈值时间值，则多模式CDR电路以第一模式工作。