公开(公告)号：US07304494B2

公开(公告)日：2007-12-04

申请号：US11098832

申请日：2005-04-04

申请人： Wilson Wong ,  Tim T Hoang ,  Sergey Y Shumarayev ,  Rakesh H Patel ,  Simardeep Maangat

发明人： Wilson Wong ,  Tim T Hoang ,  Sergey Y Shumarayev ,  Rakesh H Patel ,  Simardeep Maangat

IPC分类号： H03K17/16

CPC分类号： H03K19/017545

摘要： Circuitry and methods are provided for an LVDS-like transmitter that may be able to DC couple to a receiver having a CML termination scheme. Replacing the common mode voltage source of an LVDS transmitter with a resistive pulldown to ground may allow the transmitter to interface in a DC coupled fashion with a CML receiver. Further, the resistive pulldown may be programmable. This LVDS-like transmitter may be able to support a wider customer base by allowing it to DC couple to a wider range of termination voltage levels, such as CML termination voltage levels.

摘要翻译： 为能够将DC耦合到具有CML终止方案的接收机的类似LVDS的发射机提供电路和方法。 将具有电阻下拉到地的LVDS发射机的共模电压源替换可允许发射机以直流耦合方式与CML接收器接口。 此外，电阻下拉可以是可编程的。 这种类似LVDS的发射机可能能够通过允许其将DC耦合到更广泛的终止电压电平范围（例如CML终止电压电平）来支持更广泛的客户群。

公开(公告)号：US07680232B2

公开(公告)日：2010-03-16

申请号：US11040342

申请日：2005-01-21

申请人： Sergey Y Shumarayev ,  Rakesh H Patel ,  Wilson Wong ,  Tim T Hoang

发明人： Sergey Y Shumarayev ,  Rakesh H Patel ,  Wilson Wong ,  Tim T Hoang

IPC分类号： H04L7/00 ,  H03D3/24

CPC分类号： H03L7/0998 ,  H03L7/081 ,  H03L7/087 ,  H03L7/113 ,  H03L7/14 ,  H04L7/0025 ,  H04L7/0083 ,  H04L7/033

摘要： The disclosed invention is a technology for producing a recovered clock signal using a multi-mode clock data recovery (CDR) circuit that accommodates a flexible range operating frequencies F and consecutive identical digit requirements CID. In a first mode of operation, a controlled oscillator produces the recovered clock signal, and in a second mode of operation, a phase interpolator produces the recovered clock signal. The multi-mode CDR circuit operates in the first mode if (CID/F) is less than a threshold time value and in the second mode if (CID/F) is greater than the threshold time value.

摘要翻译： 所公开的发明是使用容纳灵活范围操作频率F和连续相同数字要求CID的多模式时钟数据恢复（CDR）电路产生恢复的时钟信号的技术。 在第一操作模式中，受控振荡器产生恢复的时钟信号，并且在第二操作模式中，相位内插器产生恢复的时钟信号。 （CID / F）小于阈值时间值，如果（CID / F）大于阈值时间值，则多模式CDR电路以第一模式工作。

公开(公告)号：US07109743B2

公开(公告)日：2006-09-19

申请号：US11148046

申请日：2005-06-07

申请人： Sergey Y Shumarayev ,  Thomas H White ,  Rakesh H Patel ,  Wilson Wong

发明人： Sergey Y Shumarayev ,  Thomas H White ,  Rakesh H Patel ,  Wilson Wong

IPC分类号： H03K17/16

CPC分类号： H03K19/17744 ,  H03K19/018585 ,  H03K19/1778 ,  H04L25/0272 ,  H04L25/0286

摘要： Programmable logic device integrated circuitry having differential I/O circuitry is provided. The differential I/O circuitry may include output drivers for providing differential digital output data signals across pairs of output lines. A user may program the I/O circuitry to accommodate different high-speed differential I/O signaling standards. The user may also program the I/O circuitry to provide a desired amount of preemphasis to the output data signals.

摘要翻译： 提供了具有差分I / O电路的可编程逻辑器件集成电路。 差分I / O电路可以包括用于在输出线对之间提供差分数字输出数据信号的输出驱动器。 用户可以对I / O电路进行编程，以适应不同的高速差分I / O信号标准。 用户还可以对I / O电路进行编程，以向输出数据信号提供期望量的预加重。

公开(公告)号：US07590207B1

公开(公告)日：2009-09-15

申请号：US11256346

申请日：2005-10-20

申请人： Sergey Y Shumarayev ,  Rakesh H Patel ,  Wilson Wong ,  Tim Tri Hoang ,  William Bereza

发明人： Sergey Y Shumarayev ,  Rakesh H Patel ,  Wilson Wong ,  Tim Tri Hoang ,  William Bereza

IPC分类号： H04L7/00

CPC分类号： H03L7/087 ,  H04J3/0688 ,  H04L7/033

摘要： A serial interface for a programmable logic device can be used as a conventional high-speed quad interface, but also allows an individual channel, if not otherwise being used, to be programmably configured as a loop circuit (e.g., a phase-locked loop). This is accomplished by disabling the data loop of clock-data recovery circuitry in the channel, and reconfiguring the reference loop to operate as a loop circuit. In addition, instead of providing a high-speed quad interface having four channels and one or more clock management units (CMUs), a more flexible interface having five or more channels can be provided, and when it is desired to use the interface as a high-speed quad interface, one or more channels can be configured as loop circuits to function as CMUs.

摘要翻译： 用于可编程逻辑器件的串行接口可以用作传统的高速四边形接口，但是也允许单独的通道（如果不另外使用）被可编程地配置为环路电路（例如，锁相环） 。 这是通过禁用通道中的时钟数据恢复电路的数据循环来实现的，并且重新配置参考环路以用作循环电路。 此外，不是提供具有四个通道的高速四边形接口和一个或多个时钟管理单元（CMU），而是可以提供具有五个或更多个通道的更灵活的接口，并且当希望将接口用作 高速四通道接口，一个或多个通道可以配置为循环电路，用作CMU。

公开(公告)号：US07804892B1

公开(公告)日：2010-09-28

申请号：US11347527

申请日：2006-02-03

申请人： Sergey Y Shumarayev ,  Rakesh H Patel

发明人： Sergey Y Shumarayev ,  Rakesh H Patel

IPC分类号： H03H7/40

CPC分类号： H04L25/03885 ,  H04L25/03057

摘要： Equalization circuitry may be implemented by cascading a plurality of equalization stages. Each equalization stage may compensate for some of the attenuation of a received data signal. Each equalization stage may also be configured to perform decision feedback equalization to remove distortion from the current bit of data signal caused by one of the preceding bits in the data signal. Each equalization stage may be controlled by a DFE coefficient that determines the amount of voltage with which to adjust the output of the equalization stage. The equalization circuitry may be implemented on a receiver that includes clock data recovery circuitry and a pipeline/deserializer for providing preceding bit values to the equalization stages.

摘要翻译： 均衡电路可以通过级联多个均衡级来实现。 每个均衡级可以补偿接收到的数据信号的一些衰减。 每个均衡级还可以被配置为执行判决反馈均衡以从数据信号中的前一位之一引起的数据信号的当前位中去除失真。 每个均衡级可以由DFE系数来控制，该DFE系数确定用于调整均衡级的输出的电压量。 均衡电路可以在包括时钟数据恢复电路和流水线/解串器的接收机上实现，用于向均衡级提供先前的位值。

公开(公告)号：US07525340B2

公开(公告)日：2009-04-28

申请号：US11230002

申请日：2005-09-19

申请人： Sergey Y Shumarayev ,  Rakesh H Patel ,  Chong H Lee

发明人： Sergey Y Shumarayev ,  Rakesh H Patel ,  Chong H Lee

IPC分类号： G09F7/38 ,  H03K19/173 ,  H03K19/177 ,  H01L25/00

CPC分类号： H03K19/17704 ,  H03K19/17732 ,  H03K19/17744

摘要： A programmable logic device (PLD) having one or more programmable logic regions and one or more conventional input/output regions additionally has one or more peripheral areas including specialized circuitry. The peripheral specialized regions, which are not connected to the remainder of the programmable logic device (and may be made on separate dies from the remainder of the programmable logic device mounted on a common substrate), and one or both of the programmable logic regions and the conventional I/O regions, have contacts for metallization traces or other interconnections to connect the peripheral specialized regions to the remainder of the programmable logic device. The same PLD can be sold with or without the specialized circuitry capability by providing or not providing the interconnections. The peripheral specialized regions may include high-speed I/O (basic, up to about 3 Gbps, and enhanced, up to about 10-12 Gbps), as well as other types of specialized circuitry.

摘要翻译： 具有一个或多个可编程逻辑区域和一个或多个常规输入/输出区域的可编程逻辑器件（PLD）还具有包括专用电路的一个或多个外围区域。 外围专用区域不连接到可编程逻辑器件的其余部分（并且可以在与安装在公共衬底上的可编程逻辑器件的其余部分分开的管芯上）制造，以及一个或两个可编程逻辑区域 常规I / O区域具有用于金属化迹线或其它互连的触点，以将外围专用区域连接到可编程逻辑器件的其余部分。 通过提供或不提供互连，可以在具有或不具有专用电路能力的情况下出售相同的PLD。 外围专业区域可能包括高速I / O（基本，高达约3 Gbps，增强，高达10-12 Gbps）以及其他类型的专用电路。

公开(公告)号：US07616657B2

公开(公告)日：2009-11-10

申请号：US11402417

申请日：2006-04-11

申请人： Sergey Shumarayev ,  Bill W Bereza ,  Chong H Lee ,  Rakesh H Patel ,  Wilson Wong

发明人： Sergey Shumarayev ,  Bill W Bereza ,  Chong H Lee ,  Rakesh H Patel ,  Wilson Wong

IPC分类号： H04J3/00

CPC分类号： H04L5/14 ,  H03K19/17744 ,  H04L27/00

摘要： High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.

摘要翻译： 可编程逻辑器件（“PLD”）上的高速串行数据收发器电路包括一些能够以高达第一，相对较低的最大数据速率的数据速率工作的通道，以及能够以数据速率操作的其他通道 达到第二个相对较高的最大数据速率。 相对低速的通道由相对低速的锁相环（“PLL”）电路服务，并且具有通常用于处理以相对低的数据速率发送的数据所需的其他电路组件。 相对高速的信道由相对高速的PLL服务，并且具有通常用于处理以相对高的数据速率传输的数据所需的其他电路部件。

公开(公告)号：US6107854A

公开(公告)日：2000-08-22

申请号：US62379

申请日：1998-04-17

申请人： Wilson Wong ,  John E. Turner ,  Thomas H. White ,  Rakesh H Patel

发明人： Wilson Wong ,  John E. Turner ,  Thomas H. White ,  Rakesh H Patel

IPC分类号： H03K5/00 ,  H03K19/003 ,  H03K19/017 ,  H03K19/0185 ,  H03H11/26

CPC分类号： H03K19/00384 ,  H03K19/01721 ,  H03K19/018585 ,  H03K2005/00078

摘要： A speed path circuit includes a reference circuit and adjustable drive components that can be turned on or off to vary the speed path in order to meet minimum delay specification for the circuit. In an embodiment, one or more differential amplifiers are used to detect the strength of example circuit elements and generate a reference signal. An optional embodiment includes a mechanism for disconnecting the reference circuit to avoid any DC current drain. The invention may be used in a wide range of integrated circuits and may also be used in a programmable logic device (PLD). Reference circuits may be disconnected from a power source by using programmable logic elements.

摘要翻译： 速度路径电路包括参考电路和可调节的驱动部件，其可以被接通或关断以改变速度路径，以便满足电路的最小延迟规范。 在一个实施例中，使用一个或多个差分放大器来检测示例电路元件的强度并产生参考信号。 可选实施例包括用于断开参考电路以避免任何直流电流消耗的机构。 本发明可以用于广泛的集成电路中，并且还可以用在可编程逻辑器件（PLD）中。 参考电路可以通过使用可编程逻辑元件与电源断开连接。

公开(公告)号：US07590174B2

公开(公告)日：2009-09-15

申请号：US11312181

申请日：2005-12-20

申请人： Wilson Wong ,  Rakesh H Patel ,  Sergey Shumarayev ,  Tin H Lai

发明人： Wilson Wong ,  Rakesh H Patel ,  Sergey Shumarayev ,  Tin H Lai

IPC分类号： H03H7/30 ,  H03H7/40 ,  H03K5/159

CPC分类号： H04B7/005 ,  H04L25/03006 ,  H04L25/061

摘要： Systems and methods for adjusting a signal received from a communication path are disclosed. A receiver can receive a signal from a communication path which attenuates at least some frequency components of the signal. The receiver can include an equalization block that adjusts at least some of the frequency content of the received signal, a signal normalization block that provides a normalized signal amplitude and/or a normalized edge slope, and a control block. In one embodiment, the control block controls frequency adjustment in the equalization block for high frequencies but not for low frequencies. For low frequency adjustment, the control block controls the normalized signal amplitude in the signal normalization block. In this manner, controlled adjustment for low frequency content is performed in the signal normalization block.

摘要翻译： 公开了一种用于调整从通信路径接收的信号的系统和方法。 接收机可以接收来自衰减信号的至少一些频率分量的通信路径的信号。 接收机可以包括调整接收信号的频率内容中的至少一些的均衡块，提供归一化信号幅度和/或归一化边沿斜率的信号归一化块以及控制块。 在一个实施例中，控制块控制用于高频而不是低频的均衡块中的频率调整。 对于低频调整，控制块控制信号归一化块中的归一化信号幅度。 以这种方式，在信号归一化块中执行低频内容的受控调整。

公开(公告)号：US07538578B2

公开(公告)日：2009-05-26

申请号：US11177034

申请日：2005-07-08

申请人： Ramanand Venkata ,  Chong H Lee ,  Rakesh H Patel

发明人： Ramanand Venkata ,  Chong H Lee ,  Rakesh H Patel

IPC分类号： H03K19/177 ,  G06F13/42

CPC分类号： H03K19/17744

摘要： A serial interface for a programmable logic device can be operated according to various communications protocols and includes both a receiver portion and a transmitter portion. The receiver portion includes at least a word or byte alignment stage, a de-skew stage, a rate compensation or matching stage, a padded protocol decoder stage (e.g., 8B/10B decoder circuitry or 64B/66B decoder circuitry), a byte deserializer stage, a byte reorder stage, and a phase compensation stage. The transmitter portion includes at least a phase compensation stage, a byte deserializer stage, and a padded protocol encoder stage (e.g., an 8B/10B encoder circuitry or 64B/66B encoder circuitry). Each stage may have multiple occurrences of relevant circuitry. Selection circuitry, such as multiplexers, selects the appropriate stages, and circuitry within each stage, for the protocol being used.

摘要翻译： 用于可编程逻辑器件的串行接口可以根据各种通信协议进行操作，并且包括接收器部分和发射器部分。 接收器部分至少包括字或字节对准级，去偏移级，速率补偿或匹配级，填充协议解码器级（例如，8B / 10B解码器电路或64B / 66B解码器电路），字节解串器 阶段，字节重排阶段和相位补偿阶段。 发射机部分至少包括相位补偿级，字节解串器级和填充协议编码器级（例如，8B / 10B编码器电路或64B / 66B编码器电路）。 每个阶段可能有多次出现相关的电路。 选择电路，例如多路复用器，为所使用的协议选择适当的阶段和每个阶段内的电路。