TOILET INSTALLATION SYSTEM AND METHOD OF INSTALLING TOILET
    1.
    发明申请
    TOILET INSTALLATION SYSTEM AND METHOD OF INSTALLING TOILET 审中-公开
    厕所安装系统及其安装方法

    公开(公告)号:US20170022695A1

    公开(公告)日:2017-01-26

    申请号:US14805713

    申请日:2015-07-22

    申请人: Timothy J. Wood

    发明人: Timothy J. Wood

    IPC分类号: E03D11/16

    CPC分类号: E03D11/16

    摘要: An aspect of the invention provides for a toilet installation system. The toilet installation system may comprise: a first set of supports configured to position a first toilet bolt hole of a toilet over a first flange bolt hole of a toilet flange; and a second set of supports configured to position an opposing second toilet bolt hole of the toilet over the second flange bolt hole of the toilet flange.

    摘要翻译: 本发明的一个方面提供了一种马桶安装系统。 马桶安装系统可以包括:第一组支撑件,其构造成将马桶的第一马桶螺栓孔定位在马桶凸缘的第一凸缘螺栓孔上; 以及第二组支撑件,其构造成将马桶的相对的第二马桶螺栓孔定位在马桶凸缘的第二凸缘螺栓孔上。

    VASCULAR PUNCTURE CLOSURE SYSTEM WITH GUIDE SHEATH STABILIZER
    2.
    发明申请
    VASCULAR PUNCTURE CLOSURE SYSTEM WITH GUIDE SHEATH STABILIZER 审中-公开
    具有导向稳定器的血管闭塞系统

    公开(公告)号:US20100179588A1

    公开(公告)日:2010-07-15

    申请号:US12353624

    申请日:2009-01-14

    IPC分类号: A61B17/10

    摘要: A guide sheath for use in guiding a vascular puncture closure device to and in registry with a vascular puncture includes a stabilization system having retention wires deployable from the sheath and engageable with the vessel wall. The retention wires pierce the vessel wall at spaced locations, proximally and distally, about the puncture and form anchors to retain the sheath in registry with the puncture.

    摘要翻译: 用于将血管穿刺闭合装置引导到血管穿刺并与注射管血管穿刺中使用的引导护套包括具有可从护套展开并可与血管壁接合的保留线的稳定系统。 保持线围绕穿刺在相邻的位置以近端和远端分开的位置刺穿血管壁,并形成锚固件,以将鞘保持与穿刺对齐。

    Method and apparatus for built-in self-repair of memory storage arrays
    4.
    发明授权
    Method and apparatus for built-in self-repair of memory storage arrays 有权
    用于存储器阵列内置自修复的方法和装置

    公开(公告)号:US06259637B1

    公开(公告)日:2001-07-10

    申请号:US09728285

    申请日:2000-12-01

    IPC分类号: G11C700

    CPC分类号: G11C29/4401 G11C29/44

    摘要: An integrated circuit device includes a memory array having a plurality of memory cells arranged in a plurality of rows and a plurality of columns. First and second redundant rows of memory cells and a first redundant column of memory cells are provided. A test circuit is coupled to the memory array and is adapted to test a plurality of memory cells coupled to each of the plurality of rows. A control circuit is coupled to the test circuit and is adapted to receive test results from the test circuit, the control circuit being adapted to respond to a detection of a defective memory cell to determine an assignment of at least one of the first and second redundant rows and first redundant column. A first register is coupled to the control circuit and adapted to receive an assignment of the first redundant row in response to a determination by the control circuit, a second register is coupled to the control circuit and adapted to receive an assignment of the first redundant column in response to a determination by the control circuit, and a third register is coupled to the control circuit and adapted to receive an assignment of the second redundant row in response to a determination by the control circuit.

    摘要翻译: 集成电路装置包括具有以多行和多列布置的多个存储单元的存储器阵列。 提供存储单元的第一和第二冗余行和存储器单元的第一冗余列。 测试电路耦合到存储器阵列,并且适于测试耦合到多个行中的每一行的多个存储器单元。 控制电路耦合到测试电路并且适于从测试电路接收测试结果,所述控制电路适于响应于有缺陷的存储器单元的检测,以确定第一和第二冗余中的至少一个的分配 行和第一冗余列。 第一寄存器耦合到控制电路并且适于响应于控制电路的确定而接收第一冗余行的分配,第二寄存器耦合到控制电路并且适于接收第一冗余列的分配 响应于控制电路的确定,并且第三寄存器耦合到控制电路,并且适于响应于控制电路的确定而接收第二冗余行的分配。

    Low profile intraluminal suturing device and method
    5.
    发明授权
    Low profile intraluminal suturing device and method 失效
    薄型腔内缝合装置及方法

    公开(公告)号:US5902311A

    公开(公告)日:1999-05-11

    申请号:US491496

    申请日:1995-06-15

    IPC分类号: A61B17/04 A61B17/00

    摘要: An improved suturing device and method is provided. The suturing device is of the type including a guide body and means on the guide body for translating at least one needle relative to the guide body. The suturing device is improved by providing a rotatable sleeve disposed over at least a distal portion of the guide body to facilitate introduction of the device to a puncture site.

    摘要翻译: 提供了一种改进的缝合装置和方法。 缝合装置的类型包括引导体和引导体上用于相对于引导体平移至少一个针的装置。 通过提供设置在引导体的至少远端部分上方的可旋转套筒来改善缝合装置,以便于将装置引入穿刺部位。

    TOILET FLANGE
    7.
    发明申请
    TOILET FLANGE 审中-公开

    公开(公告)号:US20160024775A1

    公开(公告)日:2016-01-28

    申请号:US14792843

    申请日:2015-07-07

    申请人: Timothy J. Wood

    发明人: Timothy J. Wood

    IPC分类号: E03D11/16

    CPC分类号: E03D11/16

    摘要: The present disclosure generally provides embodiments for a toilet flange. In an embodiment, the toilet flange includes a body having a toilet-facing surface, a drain-facing surface, and a drain opening therethrough and at least two chambers extending from the toilet-facing surface only partially into the body, each chamber having a fastener passageway for receiving a portion of a first fastener for coupling the body to a toilet base.

    TILE INSTALLATION GUIDE AND RELATED METHOD
    8.
    发明申请
    TILE INSTALLATION GUIDE AND RELATED METHOD 审中-公开
    TI安装指南和相关方法

    公开(公告)号:US20140230361A1

    公开(公告)日:2014-08-21

    申请号:US14063661

    申请日:2013-10-25

    申请人: Timothy J. Wood

    发明人: Timothy J. Wood

    IPC分类号: E04F21/00

    摘要: Various embodiments provide apparatuses and methods for installing tile with a tile installation guide. In some embodiments, an apparatus includes a tile installation guide comprising a guide body having a polygonal outer surface and an opening configured to surround a non-polygonal element.

    摘要翻译: 各种实施例提供了用瓦片安装指南安装瓦片的装置和方法。 在一些实施例中,一种装置包括瓦片安装引导件,其包括具有多边形外表面的引导体和被构造为围绕非多边形元件的开口。

    MECHANISM FOR MAINTAINING CACHE SOFT REPAIRS ACROSS POWER STATE TRANSITIONS
    9.
    发明申请
    MECHANISM FOR MAINTAINING CACHE SOFT REPAIRS ACROSS POWER STATE TRANSITIONS 有权
    维持电源状态转换的缓存软件维修机制

    公开(公告)号:US20120030509A1

    公开(公告)日:2012-02-02

    申请号:US12843916

    申请日:2010-07-27

    IPC分类号: G06F11/14

    摘要: A processor core includes one or more cache memories and a repair unit. The repair unit may repair locations in the cache memories identified as having errors during an initialization sequence. The repair unit may further cause information corresponding to the repair locations to be stored within one or more storages. In response to initiation of a power-down state of a given processor core, the given processor core may execute microcode instructions that cause the information from the one or more storages to be saved to a memory unit. During a recovery of the given processor core from the power-down state, the processor core may execute additional microcode instructions that cause the information to be retrieved from the memory unit, and saved to the one or more storages. The repair unit may restore repairs to the locations in the cache memories using the information.

    摘要翻译: 处理器核心包括一个或多个缓存存储器和修复单元。 修复单元可以修复在初始化序列期间被识别为具有错误的高速缓冲存储器中的位置。 维修单元还可以使得与维修位置对应的信息存储在一个或多个存储器中。 响应于给定处理器核心的掉电状态的启动,给定的处理器核心可以执行微代码指令,其使来自一个或多个存储器的信息被保存到存储器单元。 在给定处理器核心从掉电状态恢复期间,处理器核心可以执行附加的微代码指令,其使得从存储器单元检索信息,并将其保存到一个或多个存储器。 修复单元可以使用该信息恢复对高速缓冲存储器中的位置的修复。

    CENTRALIZED MBIST FAILURE INFORMATION
    10.
    发明申请
    CENTRALIZED MBIST FAILURE INFORMATION 有权
    集中MBIST失败信息

    公开(公告)号:US20110055644A1

    公开(公告)日:2011-03-03

    申请号:US12549164

    申请日:2009-08-27

    IPC分类号: G11C29/12 G06F11/27

    摘要: Failure and repair information collected during self-testing of arrays in an integrated circuit is stored in a centralized array in the integrated circuit. In that way, a centralized array can be read out to provide failure and repair information on the arrays in the integrated circuit rather than having to read from each array. In addition, the failure and repair information may also be stored in the array under test for certain of the arrays.

    摘要翻译: 在集成电路中的阵列自检期间收集的故障和修复信息存储在集成电路中的集中式阵列中。 以这种方式,可以读取集中式阵列,以提供集成电路中阵列的故障和修复信息,而不必从每个阵列读取。 此外,故障和修复信息也可能存储在被测阵列中的某些阵列中。