公开(公告)号：US20070147560A1

公开(公告)日：2007-06-28

申请号：US11318812

申请日：2005-12-27

申请人： Rami Banna ,  Tomasz Prokop ,  Long Ung ,  Dominic Yip

发明人： Rami Banna ,  Tomasz Prokop ,  Long Ung ,  Dominic Yip

IPC分类号： H04B1/10

CPC分类号： H04L25/03038 ,  H04L2025/03375 ,  H04L2025/03477 ,  H04L2025/03611

摘要： A communications circuit includes a filter module with a sampling window, a control module, and an input buffer. The control module has a ray parameter interface to obtain information regarding significant ray changes that make it desirable to re-position the sampling window. The control module determines re-positioning parameters, responsive to this information, which reflect the re-positioning of the sampling window. The input buffer obtains samples of a received signal and outputs received signal data to the filter module. The filter module obtains the re-positioning parameters from the control module, and the filter module and control module temporally re-position the sampling window in duration and/or location in accordance with the re-positioning parameters, and output a filtered chip.

摘要翻译： 通信电路包括具有采样窗口的滤波器模块，控制模块和输入缓冲器。 控制模块具有射线参数界面，以获得关于重要射线变化的信息，这使得需要重新定位采样窗口。 响应于该信息，控制模块确定重新定位参数，其反映采样窗口的重新定位。 输入缓冲器获得接收信号的样本，并将接收的信号数据输出到滤波器模块。 滤波器模块从控制模块获得重定位参数，滤波器模块和控制模块根据重定位参数在持续时间和/或位置暂时重新定位采样窗口，并输出滤波芯片。

公开(公告)号：US20070140320A1

公开(公告)日：2007-06-21

申请号：US11311003

申请日：2005-12-19

申请人： Rami Banna ,  Adriel Kind ,  Tomasz Prokop ,  Dominic Yip ,  Gongyu Zhou

发明人： Rami Banna ,  Adriel Kind ,  Tomasz Prokop ,  Dominic Yip ,  Gongyu Zhou

IPC分类号： H04B1/00 ,  H04B1/10

CPC分类号： H04L25/03038 ,  H04B1/7101

摘要： A multi-stage receiver including, in one embodiment, a sequence of processing stages. At least one of the processing stages includes a first processing block, a delay block, and a second processing block. The first processing block is adapted to receive an input signal and generate from the input signal one or more processing parameters. The delay block is adapted to generate a delayed signal. The second processing block is adapted to apply the one or more processing parameters to the delayed signal to generate an output signal. The delay block compensates for one or more processing delays associated with the generation of the one or more processing parameters by the first processing block.

摘要翻译： 在一个实施例中，多级接收机包括一系列处理级。 至少一个处理级包括第一处理块，延迟块和第二处理块。 第一处理块适于接收输入信号并从输入信号生成一个或多个处理参数。 延迟块适于产生延迟信号。 第二处理块适于将一个或多个处理参数应用于延迟信号以产生输出信号。 延迟块补偿与第一处理块生成一个或多个处理参数相关联的一个或多个处理延迟。

公开(公告)号：US08804885B2

公开(公告)日：2014-08-12

申请号：US11311003

申请日：2005-12-19

申请人： Rami Banna ,  Adriel P. Kind ,  Tomasz Prokop ,  Dominic W. Yip ,  Gongyu Zhou

发明人： Rami Banna ,  Adriel P. Kind ,  Tomasz Prokop ,  Dominic W. Yip ,  Gongyu Zhou

IPC分类号： H04B1/10

CPC分类号： H04L25/03038 ,  H04B1/7101

摘要： A multi-stage receiver including, in one embodiment, a sequence of processing stages. At least one of the processing stages includes a first processing block, a delay block, and a second processing block. The first processing block is adapted to receive an input signal and generate from the input signal one or more processing parameters. The delay block is adapted to generate a delayed signal. The second processing block is adapted to apply the one or more processing parameters to the delayed signal to generate an output signal. The delay block compensates for one or more processing delays associated with the generation of the one or more processing parameters by the first processing block.

摘要翻译： 在一个实施例中，多级接收机包括一系列处理级。 至少一个处理级包括第一处理块，延迟块和第二处理块。 第一处理块适于接收输入信号并从输入信号生成一个或多个处理参数。 延迟块适于产生延迟信号。 第二处理块适于将一个或多个处理参数应用于延迟信号以产生输出信号。 延迟块补偿与第一处理块生成一个或多个处理参数相关联的一个或多个处理延迟。

公开(公告)号：US20120076194A1

公开(公告)日：2012-03-29

申请号：US13311654

申请日：2011-12-06

申请人： Rami Banna ,  Uwe Sontowski ,  Long Ung ,  Graeme K. Woodward

发明人： Rami Banna ,  Uwe Sontowski ,  Long Ung ,  Graeme K. Woodward

IPC分类号： H04L27/01

CPC分类号： H04L25/03044 ,  H04B1/7097 ,  H04L2025/03509 ,  H04L2025/03617 ,  H04L2025/03687

摘要： In one embodiment, a receiver has a reference generator and a main equalizer. The reference generator equalizes a received signal using one or more pilot reference signals. Then, the reference generator decodes one or more predetermined data channels of the equalized signal, makes hard decisions on the data of each decoded channel, and regenerates the original coding sequence of each decoded channel. The main equalizer uses each re-encoded channel as an additional reference signal along with one or more pilot signals to equalize a time-delayed version of the received signal. In alternative embodiments, the receiver might also have a step-size generator which selects optimum step sizes from a look-up table based on the number of re-encoded channels and the power of those channels. The step size is then used by the main equalizer along with the re-encoded channels to equalize the time-delayed received signal.

摘要翻译： 在一个实施例中，接收器具有参考发生器和主均衡器。 参考发生器使用一个或多个导频参考信号来均衡接收信号。 然后，基准发生器解码均衡信号的一个或多个预定数据信道，对每个解码信道的数据作出硬判决，并重新生成每个解码信道的原始编码序列。 主均衡器使用每个重编码信道作为附加参考信号以及一个或多个导频信号来均衡接收信号的时间延迟版本。 在替代实施例中，接收机还可以具有步长生成器，其基于重新编码的信道的数量和这些信道的功率从查找表中选择最佳步长。 然后，主均衡器与重新编码的信道一起使用步长来均衡时间延迟的接收信号。

公开(公告)号：US20090080506A1

公开(公告)日：2009-03-26

申请号：US12158388

申请日：2007-01-10

申请人： Rami Banna ,  Uwe Sontowski ,  Long Ung ,  Graeme K. Woodward

发明人： Rami Banna ,  Uwe Sontowski ,  Long Ung ,  Graeme K. Woodward

IPC分类号： H04L27/01

CPC分类号： H04L25/03044 ,  H04B1/7097 ,  H04L2025/03509 ,  H04L2025/03617 ,  H04L2025/03687

摘要： In one embodiment, a receiver has a reference generator and a main equalizer. The reference generator equalizes a received signal using one or more pilot reference signals. Then, the reference generator decodes one or more predetermined data channels of the equalized signal, makes hard decisions on the data of each decoded channel, and regenerates the original coding sequence of each decoded channel. The main equalizer uses each re-encoded channel as an additional reference signal along with one or more pilot signals to equalize a time-delayed version of the received signal. In alternative embodiments, the receiver might also have a step-size generator which selects optimum step sizes from a look-up table based on the number of re-encoded channels and the power of those channels. The step size is then used by the main equalizer along with the re-encoded channels to equalize the time-delayed received signal.

摘要翻译： 在一个实施例中，接收器具有参考发生器和主均衡器。 参考发生器使用一个或多个导频参考信号来均衡接收信号。 然后，基准发生器解码均衡信号的一个或多个预定数据信道，对每个解码信道的数据作出硬判决，并重新生成每个解码信道的原始编码序列。 主均衡器使用每个重编码信道作为附加参考信号以及一个或多个导频信号来均衡接收信号的时间延迟版本。 在替代实施例中，接收机还可以具有步长生成器，其基于重新编码的信道的数量和这些信道的功率从查找表中选择最佳步长。 然后，主均衡器与重新编码的信道一起使用步长来均衡时间延迟的接收信号。

公开(公告)号：US08559573B2

公开(公告)日：2013-10-15

申请号：US11318812

申请日：2005-12-27

申请人： Rami Banna ,  Tomasz T. Prokop ,  Long Ung ,  Dominic Wing-Kin Yip

发明人： Rami Banna ,  Tomasz T. Prokop ,  Long Ung ,  Dominic Wing-Kin Yip

IPC分类号： H04B1/10

CPC分类号： H04L25/03038 ,  H04L2025/03375 ,  H04L2025/03477 ,  H04L2025/03611

摘要： A communications circuit includes a filter module with a sampling window, a control module, and an input buffer. The control module has a ray parameter interface to obtain information regarding significant ray changes that make it desirable to re-position the sampling window. The control module determines re-positioning parameters, responsive to this information, which reflect the re-positioning of the sampling window. The input buffer obtains samples of a received signal and outputs received signal data to the filter module. The filter module obtains the re-positioning parameters from the control module, and the filter module and control module temporally re-position the sampling window in duration and/or location in accordance with the re-positioning parameters, and output a filtered chip.

摘要翻译： 通信电路包括具有采样窗口的滤波器模块，控制模块和输入缓冲器。 控制模块具有射线参数界面，以获得关于重要射线变化的信息，这使得需要重新定位采样窗口。 响应于该信息，控制模块确定重新定位参数，其反映采样窗口的重新定位。 输入缓冲器获得接收信号的样本，并将接收的信号数据输出到滤波器模块。 滤波器模块从控制模块获得重定位参数，滤波器模块和控制模块根据重定位参数在持续时间和/或位置暂时重新定位采样窗口，并输出滤波芯片。

公开(公告)号：US08462839B2

公开(公告)日：2013-06-11

申请号：US13311654

申请日：2011-12-06

申请人： Rami Banna ,  Uwe Sontowski ,  Long Ung ,  Graeme K. Woodward

发明人： Rami Banna ,  Uwe Sontowski ,  Long Ung ,  Graeme K. Woodward

IPC分类号： H03H7/30

CPC分类号： H04L25/03044 ,  H04B1/7097 ,  H04L2025/03509 ,  H04L2025/03617 ,  H04L2025/03687

摘要： In one embodiment, a receiver has a reference generator and a main equalizer. The reference generator equalizes a received signal using one or more pilot reference signals. Then, the reference generator decodes one or more predetermined data channels of the equalized signal, makes hard decisions on the data of each decoded channel, and regenerates the original coding sequence of each decoded channel. The main equalizer uses each re-encoded channel as an additional reference signal along with one or more pilot signals to equalize a time-delayed version of the received signal. In alternative embodiments, the receiver might also have a step-size generator which selects optimum step sizes from a look-up table based on the number of re-encoded channels and the power of those channels. The step size is then used by the main equalizer along with the re-encoded channels to equalize the time-delayed received signal.

摘要翻译： 在一个实施例中，接收器具有参考发生器和主均衡器。 参考发生器使用一个或多个导频参考信号来均衡接收信号。 然后，基准发生器解码均衡信号的一个或多个预定数据信道，对每个解码信道的数据作出硬判决，并重新生成每个解码信道的原始编码序列。 主均衡器使用每个重编码信道作为附加参考信号以及一个或多个导频信号来均衡接收信号的时间延迟版本。 在替代实施例中，接收机还可以具有步长生成器，其基于重新编码的信道的数量和这些信道的功率从查找表中选择最佳步长。 然后，主均衡器与重新编码的信道一起使用步长来均衡时间延迟的接收信号。

公开(公告)号：US08098723B2

公开(公告)日：2012-01-17

申请号：US12158388

申请日：2007-01-10

申请人： Rami Banna ,  Uwe Sontowski ,  Long Ung ,  Graeme Woodward

发明人： Rami Banna ,  Uwe Sontowski ,  Long Ung ,  Graeme Woodward

IPC分类号： H03H7/30

CPC分类号： H04L25/03044 ,  H04B1/7097 ,  H04L2025/03509 ,  H04L2025/03617 ,  H04L2025/03687

摘要： In one embodiment, a receiver has a reference generator and a main equalizer. The reference generator equalizes a received signal using one or more pilot reference signals. Then, the reference generator decodes one or more predetermined data channels of the equalized signal, makes hard decisions on the data of each decoded channel, and regenerates the original coding sequence of each decoded channel. The main equalizer uses each re-encoded channel as an additional reference signal along with one or more pilot signals to equalize a time-delayed version of the received signal. In alternative embodiments, the receiver might also have a step-size generator which selects optimum step sizes from a look-up table based on the number of re-encoded channels and the power of those channels. The step size is then used by the main equalizer along with the re-encoded channels to equalize the time-delayed received signal.

摘要翻译： 在一个实施例中，接收器具有参考发生器和主均衡器。 参考发生器使用一个或多个导频参考信号来均衡接收信号。 然后，基准发生器解码均衡信号的一个或多个预定数据信道，对每个解码信道的数据作出硬判决，并重新生成每个解码信道的原始编码序列。 主均衡器使用每个重编码信道作为附加参考信号以及一个或多个导频信号来均衡接收信号的时间延迟版本。 在替代实施例中，接收机还可以具有步长生成器，其基于重新编码的信道的数量和这些信道的功率从查找表中选择最佳步长。 然后，主均衡器与重新编码的信道一起使用步长来均衡时间延迟的接收信号。

公开(公告)号：US20090296798A1

公开(公告)日：2009-12-03

申请号：US12295683

申请日：2007-04-05

申请人： Rami Banna ,  Mark A. Bickerstaff ,  Matthew E. Cooke ,  Adriel P. kind ,  Yi-Chen Li ,  Oliver Ridler ,  Uwe Sontowski ,  Charles N. A. Thomas ,  Long Ung ,  Koen Van den Beld ,  Benjamin J. Widdup ,  Graeme K. Woodward ,  Dominic Wing-Kin Yip ,  Gongyu Zhou

发明人： Rami Banna ,  Mark A. Bickerstaff ,  Matthew E. Cooke ,  Adriel P. kind ,  Yi-Chen Li ,  Oliver Ridler ,  Uwe Sontowski ,  Charles N. A. Thomas ,  Long Ung ,  Koen Van den Beld ,  Benjamin J. Widdup ,  Graeme K. Woodward ,  Dominic Wing-Kin Yip ,  Gongyu Zhou

IPC分类号： H03H7/40 ,  H04W4/00

CPC分类号： H04B1/70754 ,  H04B1/7097 ,  H04B2201/70701 ,  H04L25/03057 ,  H04L25/03292 ,  H04L2025/03617 ,  H04L2025/03687

摘要： In one embodiment, an HSDPA co-processor for 3GPP Release 6 Category 8 (7.2 Mb/s) HSDPA that provides all chip-rate, symbol-rate, physical-channel, and transport-channel processing for HSDPA in 90 nm CMOS. The co-processor design is scalable to all HSDPA data rates up to 14 Mb/s. The coprocessor implements an Advanced Receiver based on an NLMS equalizer, supports RX diversity and TX diversity, and provides up to 6.4 dB better performance than a typical single-antenna rake receiver. Thus, 3GPP R6 HSDPA functionality can be added to a legacy R99 modem using an HSDPA co-processor consistent with embodiments of the present invention, at a reasonable incremental cost and power.

摘要翻译： 在一个实施例中，用于3GPP版本6类别（7.2Mb / s）HSDPA的HSDPA协处理器为90nm CMOS中的HSDPA提供所有芯片速率，符号速率，物理信道和传输信道处理。 协处理器设计可扩展到高达14 Mb / s的所有HSDPA数据速率。 协处理器基于NLMS均衡器实现高级接收机，支持RX分集和TX分集，并且比典型的单天线耙式接收机提供高达6.4 dB的性能。 因此，3GPP R6 HSDPA功能可以以合理的增量成本和功率被添加到与本发明实施例一致的HSDPA协处理器的传统R99调制解调器。

公开(公告)号：US09950162B2

公开(公告)日：2018-04-24

申请号：US13037453

申请日：2011-03-01

申请人： Rami Banna ,  Andrew Botros

发明人： Rami Banna ,  Andrew Botros

IPC分类号： A61N1/36 ,  A61N1/05 ,  A61N1/372

CPC分类号： A61N1/36036 ,  A61N1/0541 ,  A61N1/37217

摘要： The present application discloses systems and methods for distributed processing of electrophysiological signals. The system may include a processor, a remote device, and an implant comprising an array of electrodes. The method may comprise the processor receiving an electrophysiological signal request from the remote device that specifies at least one electrode at the implant from which to receive an electrophysiological signal, transmitting to the implant instructions to apply a plurality of stimuli via the specified at least one electrode and, for individual stimuli in the plurality of stimuli, recording an electrophysiological signal component resulting from the stimulus. The method may also comprise the processor combining the recorded individual electrophysiological signal components to produce the electrophysiological signal and transmitting the electrophysiological signal to the remote device for further processing. In some embodiments of the method, the processor may compress the electrophysiological signal before transmitting it to the remote device.