公开(公告)号：US06715378B1

公开(公告)日：2004-04-06

申请号：US09699447

申请日：2000-10-31

申请人： Tomoaki Nakao

发明人： Tomoaki Nakao

IPC分类号： F16C126

CPC分类号： F16C1/14 ,  F16C1/12 ,  F16C2361/45 ,  F16D65/22 ,  F16D2125/60 ,  F16D2125/62 ,  F16D2125/68 ,  Y10T74/2045 ,  Y10T74/20462

摘要： A device for engaging or disengaging an end fitting of a control cable to or from a lever in a drum brake or the like is arranged to be shorter but to have a large lever ratio for the lever. A shoe is engaged with one end of a strut, and the lever is pivotally journalled to the other end of the strut while another shoe is engaged with the lever at a portion near to the journalled part. The strut has two opposed side walls and a bridge part therebetween for restraining the lever at a specified position. The lever is composed of a pair of planer members which are joined together at the proximal end, and are spaced apart from each other at the free end to form a narrow gap and at the longitudinally middle portion to form a wide gap. The narrow gap allows a cable itself of the cable to pass therethrough but to inhibit from passing therethrough and the wide gap allows a longer side of the end fitting to pass therethrough. The planar members are formed with protrusions defining a gap therebetween a size of which is smaller than the length of the longer side of the end fitting. Upon engaging the end fitting, it is inserted through the wide gap to abut against the protrusions, and then, shifted toward the free end of the lever to be engaged with the free end of the lever.

摘要翻译： 用于将控制电缆的端部配件接合或分离到鼓式制动器等中的杆的装置被布置为更短，但是对于杠杆具有大的杠杆比。 鞋与支柱的一端接合，并且杆被枢转地支撑在支柱的另一端，而另一个鞋在靠近轴颈部分的部分处与杠杆接合。 支柱具有两个相对的侧壁和其间的桥接部分，用于将杠杆限制在指定位置。 杠杆由一对平面构件构成，它们在近端处接合在一起，并且在自由端处彼此间隔开以形成窄间隙，并且在纵向中间部分处形成宽间隙。 窄间隙允许电缆的电缆本身通过，但是阻止其通过，并且宽间隙允许端配件的较长侧通过。 平面构件形成有限定其间的间隙的突起，其间的尺寸小于端配件的长边的长度。 在接合端部配件时，其通过宽间隙插入以抵靠突起，然后朝向杠杆的自由端移动以与杠杆的自由端接合。

公开(公告)号：US06331846B1

公开(公告)日：2001-12-18

申请号：US09291282

申请日：1999-04-14

申请人： Tomoaki Nakao

发明人： Tomoaki Nakao

IPC分类号： G09G336

CPC分类号： G09G3/3688 ,  G09G3/3614 ,  G09G2310/0248 ,  G09G2310/027 ,  G09G2310/0291 ,  G09G2320/0204 ,  G09G2330/023 ,  H03F3/393 ,  H03F3/45183 ,  H03F3/45744 ,  H03F2203/45212 ,  H03F2203/45588 ,  H03F2203/45614 ,  H03F2203/45616 ,  H03F2203/45681 ,  H03F2203/45724 ,  H03F2203/45726

摘要： An incidental offset voltage caused by discrepancies in material and workmanship can be averaged by (1) using two input transistors of a differential amplifier alternately, and (2) switching output signals from both the input transistors through two switches provided to an output end. Consequently, a downsized, less-power-consuming, highly-reliable differential amplifier which is insensitive to an incidental offset voltage caused by discrepancies in material and workmanship can be provided. Also, by employing such a differential amplifier, a less-power-consuming and highly reliable operational amplifier and a liquid crystal driving circuit capable of showing display of an upgraded quality can be realized.

摘要翻译： 通过（1）交替使用差分放大器的两个输入晶体管，以及（2）通过提供给输出端的两个开关将来自两个输入晶体管的输出信号切换，可以平均由材料和工艺上的差异引起的偶然的偏移电压。 因此，可以提供对由材料和工艺上的差异引起的偶然偏移电压不敏感的小型化，耗能低的高可靠性差分放大器。 此外，通过采用这样的差分放大器，可以实现能够显示升级品质显示的功耗低且可靠性高的运算放大器和液晶驱动电路。

公开(公告)号：US6160533A

公开(公告)日：2000-12-12

申请号：US659750

申请日：1996-06-06

申请人： Shigeki Tamai ,  Tomoaki Nakao

发明人： Shigeki Tamai ,  Tomoaki Nakao

IPC分类号： G02F1/133 ,  G09G3/20 ,  G09G3/36

CPC分类号： G09G3/2011 ,  G09G3/3688 ,  G09G3/3696 ,  G09G2310/0259 ,  G09G2310/027 ,  G09G2310/066

摘要： A reference voltage having a plurality of voltage levels which increase stepwise over time is supplied to source lines on a display panel through a plurality of analog switches. A value representing a number of gradation display data levels for the source lines during a horizontal scanning period is supplied as one input in to a comparison circuit. A count registered by a counter and representing a gradation clock signal is supplied as a second input. Where the count is less than the value, the analog switches remain conducted. Once the count equals to or exceeds the value, the analog switches are cut off, thus enabling the supplied reference voltage to be applied as a driving voltage to a pair of pixel electrodes. The driving voltage corresponds to the number of gradation display data levels and is held constant at the pixel electrodes for the remaining horizontal scanning period.

摘要翻译： 具有随着时间逐步增加的多个电压电平的参考电压通过多个模拟开关提供给显示面板上的源极线。 将表示水平扫描期间的源极线的灰度显示数据电平的值的值作为一个输入提供给比较电路。 作为第二输入，提供由计数器登记并表示灰度时钟信号的计数。 计数小于该值时，模拟开关保持导通。 一旦计数等于或超过该值，则模拟开关被切断，从而使提供的参考电压作为驱动电压施加到一对像素电极。 驱动电压对应于灰度显示数据电平的数量，并且在剩余的水平扫描周期的像素电极处保持恒定。

公开(公告)号：US5289518A

公开(公告)日：1994-02-22

申请号：US831341

申请日：1992-02-05

申请人： Tomoaki Nakao

发明人： Tomoaki Nakao

IPC分类号： G11C19/00 ,  H03K3/02 ,  H03K5/15 ,  H03K3/284 ,  H03K19/00

CPC分类号： H03K5/15093

摘要： A logic circuit for outputting signals corresponding to an input signal depending on a clock signal sent from an external source includes at least one synchronous flip-flop being synchronized with the clock signal, so that the flip-flop latches the input signal, and a unit for controlling an input of the clock signal to the flip-flop based on a difference between logic levels of an output signal of the flip-flop and an input signal newly latched by the flip-flop.

摘要翻译： 用于根据从外部源发送的时钟信号输出与输入信号对应的信号的逻辑电路包括与时钟信号同步的至少一个同步触发器，使得触发器锁存输入信号，并且单元 用于基于触发器的输出信号的逻辑电平和由触发器新锁存的输入信号之间的差来控制对触发器的时钟信号的输入。

公开(公告)号：US07659777B2

公开(公告)日：2010-02-09

申请号：US11882724

申请日：2007-08-03

申请人： Hiroaki Fujino ,  Tetsuya Minamiguchi ,  Michihiro Nakahara ,  Takahiro Nakai ,  Tomoaki Nakao

发明人： Hiroaki Fujino ,  Tetsuya Minamiguchi ,  Michihiro Nakahara ,  Takahiro Nakai ,  Tomoaki Nakao

IPC分类号： H03F1/02

CPC分类号： H03F3/45977 ,  H03F3/45183 ,  H03F3/45475 ,  H03F3/45753 ,  H03F2203/45101 ,  H03F2203/45136 ,  H03F2203/45212 ,  H03F2203/45534

摘要： In one embodiment of the present invention, an operational amplifier circuit, a switching element is closed and a switching element is opened. A latch circuit DL latches an output voltage of an operational amplifier and supplies a Q output corresponding to the output voltage. A control circuit supplies an offset adjustment signal to an offset adjustment input terminal OR of the operational amplifier, thereby adjusting an offset of the output voltage. The latch circuit DL latches again the output voltage thus adjusted and minutely adjusts the offset adjustment signal so as to adjust the remaining offset. Weighting is carried out in accordance with how many times latching has been carried out, and the offset of the output voltage of the operational amplifier is quantized, thereby obtaining a binary logical signal and storing the signal in the control circuit.

摘要翻译： 在本发明的一个实施例中，运算放大器电路，开关元件闭合，开关元件断开。 锁存电路DL锁存运算放大器的输出电压，并提供与输出电压相对应的Q输出。 控制电路将偏移调整信号提供给运算放大器的偏移调整输入端OR，从而调整输出电压的偏移。 锁存电路DL再次锁存如此调整的输出电压，并且精细地调整偏移调整信号，以便调整剩余的偏移。 根据执行锁存的次数进行加权，并且对运算放大器的输出电压的偏移进行量化，从而获得二进制逻辑信号并将该信号存储在控制电路中。

公开(公告)号：US20080246544A1

公开(公告)日：2008-10-09

申请号：US11882724

申请日：2007-08-03

申请人： Hiroaki Fujino ,  Tetsuya Minamiguchi ,  Michihiro Nakahara ,  Takahiro Nakai ,  Tomoaki Nakao

发明人： Hiroaki Fujino ,  Tetsuya Minamiguchi ,  Michihiro Nakahara ,  Takahiro Nakai ,  Tomoaki Nakao

IPC分类号： H03G3/30 ,  G06F3/038 ,  H03K5/125

CPC分类号： H03F3/45977 ,  H03F3/45183 ,  H03F3/45475 ,  H03F3/45753 ,  H03F2203/45101 ,  H03F2203/45136 ,  H03F2203/45212 ,  H03F2203/45534

摘要： In one embodiment of the present invention, an operational amplifier circuit, a switching element is closed and a switching element is opened. A latch circuit DL latches an output voltage of an operational amplifier and supplies a Q output corresponding to the output voltage. A control circuit supplies an offset adjustment signal to an offset adjustment input terminal OR of the operational amplifier, thereby adjusting an offset of the output voltage. The latch circuit DL latches again the output voltage thus adjusted and minutely adjusts the offset adjustment signal so as to adjust the remaining offset. Weighting is carried out in accordance with how many times latching has been carried out, and the offset of the output voltage of the operational amplifier is quantized, thereby obtaining a binary logical signal and storing the signal in the control circuit. This realizes a small-scale offset adjustment device which is capable of absorbing offset variations and which does not require a frequent refreshment process.

摘要翻译： 在本发明的一个实施例中，运算放大器电路，开关元件闭合，开关元件断开。 锁存电路DL锁存运算放大器的输出电压，并提供与输出电压相对应的Q输出。 控制电路将偏移调整信号提供给运算放大器的偏移调整输入端OR，从而调整输出电压的偏移。 锁存电路DL再次锁存如此调整的输出电压，并且精细地调整偏移调整信号，以便调整剩余的偏移。 根据执行锁存的次数进行加权，并且对运算放大器的输出电压的偏移进行量化，从而获得二进制逻辑信号并将该信号存储在控制电路中。 这实现了能够吸收偏移变化并且不需要频繁刷新过程的小尺寸偏移调整装置。

公开(公告)号：US07397278B2

公开(公告)日：2008-07-08

申请号：US11341611

申请日：2006-01-30

申请人： Tomoaki Nakao

发明人： Tomoaki Nakao

IPC分类号： H03K19/096

CPC分类号： G09G3/3685 ,  G09G3/20 ,  G09G2310/027 ,  G09G2310/0289 ,  G09G2320/0219 ,  G09G2330/021 ,  H03K3/356113 ,  H03K19/01855

摘要： A P-channel MOS transistor and an N-channel MOS transistor are respectively controlled by a first control signal and a second control signal. The first control signal CTL1 and the second control signal CTL2 are independent from each other. The second control signal CTL2 is generated by a NOR circuit 2 to which a data signal DATA and a third control signal CTL3 are inputted. A load capacitor C1 which samples the first electric potential or the GND electric potential is configured by a gate capacitance of another MOS transistor.

摘要翻译： P沟道MOS晶体管和N沟道MOS晶体管分别由第一控制信号和第二控制信号控制。 第一控制信号CTL1和第二控制信号CTL2彼此独立。 第二控制信号CTL2由输入数据信号DATA和第三控制信号CTL 3的NOR电路2产生。 对第一电位或GND电位进行采样的负载电容器C 1由另一MOS晶体管的栅极电容构成。

公开(公告)号：US20070132702A1

公开(公告)日：2007-06-14

申请号：US11633429

申请日：2006-12-05

申请人： Noriyuki Kajihara ,  Hiroaki Fujino ,  Tomoaki Nakao ,  Yukihisa Orisaka ,  Eisaku Miyazaki ,  Michihiro Nakahara ,  Yasuhiro Nishida ,  Masahiko Monomohshi

发明人： Noriyuki Kajihara ,  Hiroaki Fujino ,  Tomoaki Nakao ,  Yukihisa Orisaka ,  Eisaku Miyazaki ,  Michihiro Nakahara ,  Yasuhiro Nishida ,  Masahiko Monomohshi

IPC分类号： G09G3/36

CPC分类号： G09G3/3696 ,  G09G3/006 ,  G09G3/3688 ,  G09G2300/0426 ,  G09G2320/02

摘要： A display driving integrated circuit includes: a tone display reference voltage generating circuit for generating 64 tone display reference voltages by resistive division on the basis of a predetermined reference voltage; D/A conversion circuits each for performing an analog conversion with respect to display data on the basis of the 64 tone display reference voltages; and 64 reference voltage wires provided in parallel, via which the 64 tone display reference voltages are supplied to the D/A conversion circuits, respectively. The 64 reference voltage wires are provided so that a potential difference corresponds to two tones or more between adjacent two reference voltage wires.

摘要翻译： 显示驱动集成电路包括：音调显示参考电压产生电路，用于根据预定参考电压通过电阻划分产生64个音调显示参考电压; D / A转换电路，用于基于64个音调显示参考电压来执行关于显示数据的模拟转换; 以及并联提供的64个参考电压线，64个音调显示基准电压分别被提供给D / A转换电路。 提供64个参考电压线，使得电位差对应于相邻的两个参考电压线之间的两个音调或更多。

公开(公告)号：US06437716B2

公开(公告)日：2002-08-20

申请号：US09731736

申请日：2000-12-08

申请人： Tomoaki Nakao

发明人： Tomoaki Nakao

IPC分类号： H03M106

CPC分类号： G09G3/3696 ,  G09G2320/0606 ,  G09G2320/0673

摘要： There is provided a gray scale display reference voltage generating circuit that can change a gamma correction characteristic in accordance with a liquid crystal material and LCD panel characteristics. Resistor elements R0 through R7 have a resistance ratio for gamma correction and generate gamma-corrected intermediate voltages on the basis of voltages across both input terminals V0 and V64. A gamma correction adjustment circuit 42 adjusts the gamma-corrected intermediate voltages upward or downward on the basis of adjustment data latched in a data latch circuit 43. By thus supplying the adjustment data corresponding to the liquid crystal material and the LCD panel characteristics to the data latch circuit 43, the gamma correction characteristic can be changed in accordance with the liquid crystal material and the LCD panel characteristics without modifying the design of a source driver.

摘要翻译： 提供了可以根据液晶材料和LCD面板特性改变伽马校正特性的灰度显示参考电压产生电路。 电阻元件R0至R7具有用于伽马校正的电阻比，并且基于两个输入端子V0和V64上的电压产生伽马校正的中间电压。 伽马校正调整电路42基于锁存在数据锁存电路43中的调整数据，向上或向下调整伽马校正的中间电压。通过这样将对应于液晶材料的调节数据和LCD面板特性提供给数据 锁存电路43，可以根据液晶材料和LCD面板特性改变伽马校正特性，而不改变源极驱动器的设计。

公开(公告)号：US06373419B1

公开(公告)日：2002-04-16

申请号：US09461810

申请日：1999-12-16

申请人： Tomoaki Nakao

发明人： Tomoaki Nakao

IPC分类号： H03M178

CPC分类号： G09G3/3688 ,  G09G2310/027 ,  H03M1/76

摘要： A standard voltage generating circuit produces 2(N−1)+1 mutually different standard voltages. A selector circuit stores standard voltage pairs so that each of the digital signals corresponds to one of the standard voltage pairs. No standard voltage pairs produce the same mean value. Upon reception of an input digital signal, the selector circuit selects one of the standard voltage pairs which corresponds to the input digital signal and provides the standard voltages of the selected pair for output. The standard voltages provided for output by the selector circuit are supplied to a voltage follower circuit which provides an output voltage having a mean value of the input standard voltages. In a DA converter and a liquid crystal driving device incorporating the DA converter, despite a possible increase in the number of voltages required for a display of more colors and more half-tones, large increases in the number of circuit arrangement elements can be avoided and increases in manufacturing cost can be restrained, allowing the device to be built in a more compact size.

摘要翻译： 标准电压发生电路产生2（N-1）+1个相互不同的标准电压。 选择器电路存储标准电压对，使得每个数字信号对应于一个标准电压对。 没有标准电压对产生相同的平均值。 在接收到输入数字信号时，选择器电路选择对应于输入数字信号的一个标准电压对，并提供所选择的一对的标准电压以供输出。 提供给选择器电路输出的标准电压被提供给电压跟随器电路，其提供具有输入标准电压的平均值的输出电压。 在DA转换器和包含DA转换器的液晶驱动装置中，尽管可以增加显示更多颜色和更多半色调所需的电压数量，但是可以避免电路布置元件的数量的大幅增加， 可以抑制制造成本的增加，从而允许以更紧凑的尺寸构建装置。